edaa66bbed
boards: add Lambdaconcept's PCIe Screamer (R02)
2019-12-06 18:20:59 +01:00
a8635c48a4
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:15:08 +01:00
30a18808ad
boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 15:58:06 +01:00
23c33cfa99
build: automatically add keep attribute to signals with timing constraints.
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Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.
2019-12-06 15:41:15 +01:00
4c9af635d2
build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands
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Additional sdc/qsf commands can be added from the design like:
platform.sdc_additional_commands.append("create_clock ...")
platform.sdc_additional_commands.append("set_false_path ...")
2019-12-06 15:19:07 +01:00
22e6f5ac1d
build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed.
2019-12-06 12:57:59 +01:00
8fb3f9a90d
build/lattice: cleanup/simplify (no functional changes)
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icestorm still need to be cleaned up
2019-12-06 12:54:52 +01:00
946478a71e
build/lattice: cleanup/simplify
2019-12-06 12:13:20 +01:00
60edca2345
build/microsemi: cleanup/simplify (no functional change)
2019-12-06 12:12:43 +01:00
50fdc5ce41
build/altera: cleanup/simplify (no functional change)
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Altera build backend was a bit messy and needed some cleanup to ease future maintenance and new features.
2019-12-06 11:08:46 +01:00
b17dfafa55
Merge pull request #313 from mmicko/yosys_ise_flow_fix
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Yosys - ISE flow fix
2019-12-05 19:05:44 -08:00
8d90f4e97b
build/xilinx/vivado: use VHDL 2008 as default
2019-12-03 15:27:20 +01:00
cfd17321e2
targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed)
2019-12-03 10:11:15 +01:00
201d60f37a
targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16)
2019-12-03 09:05:52 +01:00
6b82064723
targets: uniformize, improve presentation
2019-12-03 08:58:01 +01:00
718f69953b
README: fix LitePCIe Travis-CI link
2019-12-02 11:03:42 +01:00
6de20f185a
soc/interconnect/csr: add fields support for CSRStorage's write simulation method
2019-12-02 09:44:44 +01:00
2567a0ae1d
soc/cores/gpio: add GPIO Tristate
2019-12-01 21:26:37 +01:00
d702c0fe35
setup.py: update long_description
2019-11-30 19:30:50 +01:00
c9665aed38
README.md: use litex logo
2019-11-30 19:23:34 +01:00
82819dd536
README: switch to Markdown
2019-11-30 19:18:47 +01:00
90f9ffc505
Merge pull request #311 from kbeckmann/trellis_cabga256
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trellis: Support the CABGA256 package
2019-11-29 19:05:56 -08:00
f411d6d362
trellis: Support the CABGA256 package
2019-11-30 02:50:41 +01:00
783dfa508c
Properly select family for those currently supported
2019-11-29 19:11:22 +01:00
6560911df2
Integrate with latest yosys changes
2019-11-29 17:12:08 +01:00
3d20442f6f
Merge pull request #310 from xobs/spi-flash-mode3-doc
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spi_flash: correct documentation on SPI mode
2019-11-25 21:01:17 +01:00
581c23725e
spi_flash: correct documentation on SPI mode
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The SPI mode is actually mode3, since the output value is updated on the
falling edge of CLK and the input value is updated on the rising edge.
This also clarifies some of the documentation based on experience with
the core.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-11-25 12:35:13 +08:00
de205d4a84
tools/remote/comm_udp: only use one socket
2019-11-22 15:28:35 +01:00
bdaca40fe4
build/generic_platform: avoid duplicate in GenericPlatform.sources
2019-11-22 15:28:07 +01:00
6883a43680
soc/cores/clock: change drp_locked to CSRStatus and connect it :)
2019-11-20 19:37:16 +01:00
36107cdfd7
soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal
2019-11-20 19:24:40 +01:00
e8e70b164a
Merge pull request #309 from antmicro/mmcm-fix
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soc/cores/clock: add lock reg and assign reset
2019-11-20 19:20:15 +01:00
fd14b76594
soc/cores/clock: add lock reg and assign reset
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It was necessary to add drp_locked CSR for reading LOCK signal from
MMCM. Additionally, input signal RESET from MMCM was not driven by
any signal to do a proper reset of MMCM module thus it was impossible
to perform entirely correct dynamic clock reconfiguration.
2019-11-20 16:22:49 +01:00
04017519c8
soc/interconnect/axi: add Wishbone2AXILite
2019-11-20 12:32:22 +01:00
4b073a440a
test/test_axi: cosmetic
2019-11-20 11:22:39 +01:00
d905521185
build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository
2019-11-19 09:11:11 +01:00
02bfda5e38
Merge pull request #308 from gsomlo/gls-sdram-init
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soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
2019-11-18 18:24:35 +01:00
3ef13fd27a
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
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Enable SDRAM to be initialized when csr_data_width > 8 bits.
Currently, csr_data_width up to 32 bits is supported.
Read leveling tested with csr_data_width [8, 16, 32] on the
ecp5-versa5g and trellisboard (using yosys/trellis/nextpnr),
and on the nexys4ddr (using Vivado).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-18 09:00:19 -05:00
1efb18f1ea
soc/interconnect/packet/Depacketizer: another simplifcation pass
2019-11-18 09:06:56 +01:00
af52203c00
soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state
2019-11-17 11:57:14 +01:00
8272a00d6e
soc/interconnect/packet/Depacketizer: replace no_payload with sink_d.last
2019-11-17 11:50:09 +01:00
6059712794
test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
2019-11-16 14:39:18 +01:00
9642893371
test/test_packet: add randomness on valid input, fix corner-cases on Packetizer
2019-11-16 08:49:04 +01:00
888fd55bd8
Merge pull request #307 from sergachev/master
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change >512 B CSR memory exception to a warning
2019-11-15 18:17:35 +01:00
2f2cfc9951
soc/interconnect/packet: fix synthesis (synthesis tools can do all sort of optimizations, but we still need to provide valid verilog :))
2019-11-15 16:19:05 +01:00
444ae951e9
change >512 B CSR memory exception to a warning
2019-11-15 15:34:12 +01:00
31661e9e2d
soc/interconnect/packet: connect error/last_be only present on both sink and source
2019-11-15 14:57:31 +01:00
2946581e50
soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple
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To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
2019-11-15 14:39:55 +01:00
33c4d961b5
test/test_packet: add 32/64/128-bit loopback tests (passing :))
2019-11-15 11:37:52 +01:00
824faf9722
test/test_packet: prepare for testing dw > 8-bit
2019-11-15 11:32:42 +01:00
Florent Kermarrec
Tim Ansell
Konrad Beckmann
Miodrag Milanovic
Sean Cross
Pawel Czarnecki
Gabriel Somlo
Ilia Sergachev