Sebastien Bourdeauducq
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c273866b08
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fhdl: support expressions in instance ports
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2012-09-22 20:51:10 +02:00 |
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Sebastien Bourdeauducq
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2fc9cae88a
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fhdl: support inverted clock ports in instances
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2012-09-22 20:50:49 +02:00 |
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Sebastien Bourdeauducq
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2e14569b5c
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fhdl/verilog: sort clock domains by name
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2012-09-11 10:00:03 +02:00 |
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Sebastien Bourdeauducq
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9a18a9df3f
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fhdl: list signals in execution order
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2012-09-11 09:59:37 +02:00 |
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Sebastien Bourdeauducq
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e16353a281
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Multi-clock design support + new instance API
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2012-09-10 23:45:02 +02:00 |
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Sebastien Bourdeauducq
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8de192dfbd
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x.bv.width -> len(x)
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2012-07-13 18:32:54 +02:00 |
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Sebastien Bourdeauducq
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7f47a2568a
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fhdl: remove _StatementList
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2012-07-13 17:07:56 +02:00 |
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Sebastien Bourdeauducq
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ed27783a53
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fhdl: arrays (TODO: use correct BV for intermediate signals)
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2012-07-09 15:16:38 +02:00 |
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Sebastien Bourdeauducq
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398ece8fe2
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fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
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2012-04-30 16:38:40 -05:00 |
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Sebastien Bourdeauducq
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2a4e49e381
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fhdl: phase out pads
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2012-04-02 19:21:43 +02:00 |
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Sebastien Bourdeauducq
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623e8e436a
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fhdl/verilog: do not attempt to initialize instance and mem output signals
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2012-04-02 12:59:42 +02:00 |
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Sebastien Bourdeauducq
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f3ae22f488
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fhdl/verilog: initialize internal read-only signals with their reset values
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2012-04-01 16:39:11 +02:00 |
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Sebastien Bourdeauducq
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90184b22d2
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fhdl/verilog: fix signed constant conversion
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2012-03-06 16:45:44 +01:00 |
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Sebastien Bourdeauducq
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a1ad30faab
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fhdl/verilog: properly connect instance inouts
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2012-02-17 11:08:41 +01:00 |
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Sebastien Bourdeauducq
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ca7056b07f
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fhdl: support forwarding of bidirectional signals from instance ports
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2012-02-16 18:34:32 +01:00 |
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Sebastien Bourdeauducq
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1eb348c573
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fhdl: do not attempt slicing non-array signals to keep Verilog happy
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2012-02-06 18:07:02 +01:00 |
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Sebastien Bourdeauducq
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5405a83ff9
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fhdl: memories working
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2012-01-27 20:22:17 +01:00 |
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Sebastien Bourdeauducq
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a5bd111370
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fhdl/verilog: clean up signal classification and support memory descriptions
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2012-01-27 16:54:48 +01:00 |
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Sebastien Bourdeauducq
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d3d5b481fe
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Include fragment pads in pre-naming dictionary
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2012-01-20 22:59:40 +01:00 |
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Sebastien Bourdeauducq
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e9be3241f6
|
Fix instance support
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2012-01-20 22:36:17 +01:00 |
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Sebastien Bourdeauducq
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e4f531a739
|
Include unused I/Os in pre-naming dictionary and register signals with name_override
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2012-01-20 22:20:32 +01:00 |
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Sebastien Bourdeauducq
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4eac60d181
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New naming system: second attempt
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2012-01-19 18:25:25 +01:00 |
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Sebastien Bourdeauducq
|
bdde97f5fd
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New naming system beginning to work
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2012-01-16 18:42:55 +01:00 |
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Sebastien Bourdeauducq
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ab8e08a2ed
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fhdl: new naming system (broken)
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2012-01-16 18:09:52 +01:00 |
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Sebastien Bourdeauducq
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aa8b8da684
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fhdl: allow None statements
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2012-01-15 17:45:54 +01:00 |
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Sebastien Bourdeauducq
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7b395b565e
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verilog: split comb block, use assign statements
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2012-01-07 12:19:06 +01:00 |
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Sebastien Bourdeauducq
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f209bf6b33
|
convtools -> tools
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2012-01-07 00:39:28 +01:00 |
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Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
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Sebastien Bourdeauducq
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8a394f9159
|
verilog: comb reset
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2011-12-22 00:04:53 +01:00 |
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Sebastien Bourdeauducq
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4d6be55e9f
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verilog: break down Convert function
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2011-12-21 23:08:50 +01:00 |
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Sebastien Bourdeauducq
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26e0b817e8
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verilog: ignore variable property in combinatorial block
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2011-12-21 23:00:36 +01:00 |
|
Sebastien Bourdeauducq
|
7456195775
|
Consistent names
|
2011-12-21 22:57:07 +01:00 |
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Sebastien Bourdeauducq
|
6f8a6db40a
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verilog: get the simulator to run the combinatorial process at the beginning
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2011-12-17 15:20:22 +01:00 |
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Sebastien Bourdeauducq
|
ec47394012
|
verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
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Sebastien Bourdeauducq
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ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
|
fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
|
Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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c840848dba
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verilog: use blocking assignment in combinatorial process
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2011-12-13 14:09:12 +01:00 |
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Sebastien Bourdeauducq
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a72faaecdd
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fhdl: allow a namespace to be specified for Verilog conversion
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2011-12-13 00:24:40 +01:00 |
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Sebastien Bourdeauducq
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eee6980a36
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fhdl: support Constant parameters for Verilog conversion
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2011-12-11 20:17:51 +01:00 |
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Sebastien Bourdeauducq
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a49ecc4331
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fhdl: pad support in fragments
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2011-12-10 20:25:24 +01:00 |
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Sebastien Bourdeauducq
|
fa63cc1ec8
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fhdl: replication support
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2011-12-09 13:11:34 +01:00 |
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Sebastien Bourdeauducq
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b0c5b74c22
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verilog: handle default in case statements
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2011-12-08 23:04:20 +01:00 |
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Sebastien Bourdeauducq
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bf021efa2b
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verilog: fix unary operator conversion
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2011-12-08 21:15:24 +01:00 |
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Sebastien Bourdeauducq
|
1b637cea61
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Instance support
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2011-12-08 16:35:32 +01:00 |
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Sebastien Bourdeauducq
|
0e8d894a35
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Variable conversion
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2011-12-05 22:00:06 +01:00 |
|
Sebastien Bourdeauducq
|
4340680704
|
Cleanup
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2011-12-05 19:25:32 +01:00 |
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Sebastien Bourdeauducq
|
ec51f09c98
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Case support + register bank generator
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2011-12-05 17:43:56 +01:00 |
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Sebastien Bourdeauducq
|
e099f4d52f
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Reset insertion
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2011-12-04 22:41:50 +01:00 |
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Sebastien Bourdeauducq
|
cd8544c758
|
Verilog generator
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2011-12-04 22:26:32 +01:00 |