Sebastien Bourdeauducq
|
bfcd4e636b
|
fhdl: handle negative constants correctly
|
2012-03-08 20:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
Sebastien Bourdeauducq
|
678a89d572
|
sim: fix zero encoding
|
2012-03-08 15:34:08 +01:00 |
|
Sebastien Bourdeauducq
|
decbd069fa
|
sim: fix message debug formatting
|
2012-03-08 15:27:35 +01:00 |
|
Sebastien Bourdeauducq
|
98e96b3952
|
sim: make initialization cycle optional (selectable by function attribute)
|
2012-03-06 19:43:59 +01:00 |
|
Sebastien Bourdeauducq
|
8160ced2e9
|
sim: memory access
|
2012-03-06 19:29:39 +01:00 |
|
Sebastien Bourdeauducq
|
db8f8bf2e3
|
fhdl: register memory objects with namespace
|
2012-03-06 18:33:44 +01:00 |
|
Sebastien Bourdeauducq
|
6f829c7afc
|
sim: support for signed numbers
|
2012-03-06 16:46:18 +01:00 |
|
Sebastien Bourdeauducq
|
90184b22d2
|
fhdl/verilog: fix signed constant conversion
|
2012-03-06 16:45:44 +01:00 |
|
Sebastien Bourdeauducq
|
9da512dbf5
|
sim: VCD generation
|
2012-03-06 15:26:04 +01:00 |
|
Sebastien Bourdeauducq
|
22b3c11b93
|
sim: clean startup/shutdown
|
2012-03-06 15:00:02 +01:00 |
|
Sebastien Bourdeauducq
|
06de17b16c
|
sim: remove temporary files and socket
|
2012-03-06 14:20:26 +01:00 |
|
Sebastien Bourdeauducq
|
7230508e7c
|
fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
|
2012-03-06 14:18:22 +01:00 |
|
Sebastien Bourdeauducq
|
2c375e900f
|
sim: remove default sockaddr
|
2012-03-06 13:58:49 +01:00 |
|
Sebastien Bourdeauducq
|
8d16fde48c
|
fhdl: add simulation functions in fragment
|
2012-03-06 13:58:22 +01:00 |
|
Sebastien Bourdeauducq
|
aac9752558
|
sim: basic functionality working
|
2012-03-05 20:31:41 +01:00 |
|
Sebastien Bourdeauducq
|
29859acc34
|
sim: two way IPC working
|
2012-03-04 19:17:03 +01:00 |
|
Sebastien Bourdeauducq
|
8586daf2dd
|
sim: IPC module (lacks str/int encoding)
|
2012-03-03 18:55:38 +01:00 |
|
Sebastien Bourdeauducq
|
1b8cb5b46c
|
bus/dfi: fix multiphase naming
|
2012-02-19 17:57:04 +01:00 |
|
Sebastien Bourdeauducq
|
d8d4e81b6e
|
bank/csrgen: fix RE generation
|
2012-02-18 18:56:18 +01:00 |
|
Sebastien Bourdeauducq
|
55a265d967
|
bank: add RE signal for registers made of fields
|
2012-02-17 23:52:06 +01:00 |
|
Sebastien Bourdeauducq
|
92dfbb92dd
|
bus: add interconnect statements function
|
2012-02-17 23:51:32 +01:00 |
|
Sebastien Bourdeauducq
|
f995e8b92e
|
fhdl: check we pass BV to signals
|
2012-02-17 23:50:54 +01:00 |
|
Sebastien Bourdeauducq
|
a1ad30faab
|
fhdl/verilog: properly connect instance inouts
|
2012-02-17 11:08:41 +01:00 |
|
Sebastien Bourdeauducq
|
ca7056b07f
|
fhdl: support forwarding of bidirectional signals from instance ports
|
2012-02-16 18:34:32 +01:00 |
|
Sebastien Bourdeauducq
|
c08687b9c6
|
bus/dfi: filter signals by direction
|
2012-02-15 21:48:05 +01:00 |
|
Sebastien Bourdeauducq
|
ef7aea0f31
|
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
|
2012-02-15 18:23:31 +01:00 |
|
Sebastien Bourdeauducq
|
fa9cf3e466
|
bus: add DFI
|
2012-02-15 18:09:14 +01:00 |
|
Sebastien Bourdeauducq
|
91e279ee04
|
bank/csrgen: use new bus API
|
2012-02-15 16:42:17 +01:00 |
|
Sebastien Bourdeauducq
|
af5230c8ee
|
bus: fix simple interconnect
|
2012-02-15 16:42:05 +01:00 |
|
Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
|
2012-02-15 16:30:16 +01:00 |
|
Sebastien Bourdeauducq
|
46b1f74e98
|
bus/asmibus/hub: forward data and tag_call
|
2012-02-14 14:00:17 +01:00 |
|
Sebastien Bourdeauducq
|
0c214b484e
|
Use double quotes for all strings
|
2012-02-14 13:12:43 +01:00 |
|
Sebastien Bourdeauducq
|
e11d9b9322
|
bus/wishbone2asmi: cache hits working
|
2012-02-13 23:11:16 +01:00 |
|
Sebastien Bourdeauducq
|
1662e1b3bc
|
corelogic: support reverse in displacer/chooser
|
2012-02-13 23:10:27 +01:00 |
|
Sebastien Bourdeauducq
|
264be80f2d
|
Fix syntax errors and other stupid problems
|
2012-02-13 22:28:02 +01:00 |
|
Sebastien Bourdeauducq
|
8a61d9d121
|
bus/csr: Rename a->adr d->dat to be consistent with the other buses
|
2012-02-13 21:46:39 +01:00 |
|
Sebastien Bourdeauducq
|
060426cb59
|
bus/wishbone2asmi: set WM, and send 0 when inactive
|
2012-02-13 16:49:43 +01:00 |
|
Sebastien Bourdeauducq
|
cad9d3b960
|
bus: Wishbone to ASMI caching bridge (untested)
|
2012-02-13 16:29:38 +01:00 |
|
Sebastien Bourdeauducq
|
244bf17db7
|
corelogic/misc: displacer + chooser
|
2012-02-11 20:57:08 +01:00 |
|
Sebastien Bourdeauducq
|
e10e4360f3
|
corelogic/misc/multimux: less confusing variable name
|
2012-02-11 20:56:51 +01:00 |
|
Sebastien Bourdeauducq
|
7894411418
|
bus/asmibus: fix typo
|
2012-02-11 20:56:01 +01:00 |
|
Sebastien Bourdeauducq
|
28b0c340af
|
corelogic/record: add to_signal convenience function
|
2012-02-11 20:55:23 +01:00 |
|
Sebastien Bourdeauducq
|
e62ac1d3a1
|
corelogic/misc: contiguous split
|
2012-02-11 11:52:15 +01:00 |
|
Sebastien Bourdeauducq
|
ef436a1ec9
|
bus/asmibus: add get_slots, fix get_fragment
|
2012-02-10 17:49:06 +01:00 |
|
Sebastien Bourdeauducq
|
945d655d45
|
bus: ASMI hub (untested)
|
2012-02-10 15:21:04 +01:00 |
|
Sebastien Bourdeauducq
|
47883675db
|
bus/wishbone2csr: truncate WB data
|
2012-02-06 18:43:34 +01:00 |
|
Sebastien Bourdeauducq
|
1eb348c573
|
fhdl: do not attempt slicing non-array signals to keep Verilog happy
|
2012-02-06 18:07:02 +01:00 |
|
Sebastien Bourdeauducq
|
fcd6583cbb
|
bank: event manager
|
2012-02-06 17:39:32 +01:00 |
|
Sebastien Bourdeauducq
|
3a2a0c4dd8
|
bank: support registers larger than the bus word width
|
2012-02-06 16:15:27 +01:00 |