f731b36c9b
build/vhd2v_converter.py: allows users to pass a list of libraries files to compile before convert HDL.
2024-11-09 07:55:18 +01:00
8b4949edcd
Merge pull request #2115 from CKeilbar/soc-region-check-fix
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Fix SOC region range check
2024-11-06 22:29:05 +01:00
de9d3ab314
soc/cores/cpu/urv: Add DataBusToWishbone and use it.
2024-11-06 21:59:11 +01:00
2b3913982c
soc/cores/cpu/urv: Add InstructionBusToWishbone and use it.
2024-11-06 21:49:39 +01:00
1204cfda9d
soc/cores/cpu/urv: Fix add_sources.
2024-11-05 17:33:32 +01:00
20b0e98fe0
cpu/urv: Fix Instruction Bus conversion to Wishbone and only keep it now that working.
2024-11-05 17:19:13 +01:00
e9613499ea
Fix SOC region range check
2024-11-04 12:01:29 -08:00
0170462fe8
soc/cores/jtag: Fix/Test p_init/p_INIT workaround.
2024-11-04 14:34:28 +01:00
3f3249cdf0
Merge pull request #2113 from trabucayre/toolchain_diamond_sdc
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litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:53:48 +01:00
47e8b0273f
litex/build/lattice/diamond, platform: allows users to add custom sdc files
2024-11-04 12:42:38 +01:00
175e63ac4c
soc/cores/jtag: Add p_INIT/p_init workaround on ECP5JTAG to support Diamond and Trellis toolchains without manual changes.
2024-11-04 12:40:39 +01:00
4368d5a9ed
test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed.
2024-10-28 21:51:42 +01:00
61ab30a739
soc/cores/jtag: Revert p_INIT since not tested.
2024-10-28 20:05:47 +01:00
10184ad325
Merge pull request #2097 from trabucayre/build_diamond_addition
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Build diamond addition
2024-10-28 20:05:01 +01:00
23df960859
Merge pull request #2102 from Dolu1990/vexiiriscv-macsg
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Vexiiriscv update
2024-10-28 20:03:06 +01:00
dd092863f8
Merge branch 'master' into vexiiriscv-macsg
2024-10-28 20:02:56 +01:00
18714dfca3
Merge pull request #2104 from andelf/fix/ws2812-of-1-led
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Fixes #2103 : calculate memory depth for WS2812
2024-10-28 19:53:25 +01:00
59fc1caac4
Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi
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vexiiriscv: add options and conditions
2024-10-25 14:26:02 +02:00
773fb34079
vexiiriscv: have opensbi behind a option
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this way opensbi things are only activated,
when a linux variant is used.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-25 13:40:20 +02:00
8c7e510473
Fixes #2103 : calculate memory depth for WS2812
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See-also: https://github.com/m-labs/migen/pull/295
2024-10-25 11:48:57 +08:00
24db36ced5
Merge remote-tracking branch 'origin/master' into wuff
2024-10-24 16:02:52 +02:00
375940ad7d
soc/core/vexiiriscv: add macsg support (dma based ethernet)
2024-10-24 16:00:51 +02:00
c1225736a8
Merge pull request #2098 from enjoy-digital/urv
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Add initial uRV CPU support.
2024-10-17 19:45:44 +02:00
5f463dba87
CHANGES.md: Update.
2024-10-17 17:45:50 +02:00
aab8912f5a
soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU.
2024-10-17 17:44:40 +02:00
9449d25911
soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory.
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- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
- Correctly handle dm bus wishbone adaptation (Added FIFO).
2024-10-17 16:54:20 +02:00
edb56e73aa
soc/cores/cpu: Add initial uRV CPU support (not yet working).
2024-10-16 22:24:07 +02:00
06f9f9780d
litex/soc/cores/jtag.py: lattice target: INIT -> init (otherwise fails with diamond)
2024-10-16 13:47:42 +02:00
ea81314866
build/lattice/diamond.py,platform.py: allows adding custom strategy
2024-10-16 13:46:43 +02:00
331e1938c9
build/lattice/diamond.py,platform.py: allows adding lattice's IPs
2024-10-16 13:45:57 +02:00
c4943c1c5d
build/lattice/diamond.py: allows adding addition ldf commands in tcl
2024-10-16 13:44:20 +02:00
c82fddf635
CHANGES.md: Update.
2024-10-15 12:54:37 +02:00
d5e4f9e975
soc/core/vexiiriscv : bring back xilinx support
2024-10-15 09:36:32 +02:00
7f04cafe08
soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location required by SGMII
2024-10-10 17:28:29 +02:00
2935b7afb1
soc/cores/cpu/zynqmp/core.py: added missing pps signals
2024-10-10 17:26:35 +02:00
dc3364a3c7
CHANGES.md: Update.
2024-10-09 16:42:05 +02:00
01c7a78f67
Merge pull request #2095 from trabucayre/zynqmp_ethernet_sgmii
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soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with optional PTP support
2024-10-09 16:38:33 +02:00
ddb8d16381
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with option PTP support
2024-10-09 16:14:31 +02:00
34b98ab578
Merge pull request #2093 from mgaggero/feature-alpine-linux
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Fixes #2092 : provides support for riscv gcc installation on Alpine Linux.
2024-10-09 06:32:05 +02:00
e148650279
Fixes #2092 : provides support for riscv gcc installation on Alpine
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Linux.
2024-10-08 20:46:38 +02:00
bc3e90c93a
Merge pull request #2090 from VOGL-electronic/efinix_iobank
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build: efinix: use ifacewriter to set bank voltage
2024-10-08 09:54:20 +02:00
d26994916d
build: efinix: use ifacewriter to set bank voltage
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use efinix python api to set bank voltage,
instead of editing the peri.xml file.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-08 09:05:04 +02:00
9ad5d21231
Merge pull request #2089 from VOGL-electronic/efinix_tristate_fix
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build: efinix: Tristate fix
2024-10-07 11:06:26 +02:00
4fcae9f3c7
build: efinix: Tristate fix
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fix efinix Tristate by adding size to add_iface_io().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-07 10:15:38 +02:00
64cf925b39
soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported.
2024-10-02 17:10:08 +02:00
5e897752b7
soc/intergration/soc/add_pcie: Add new status_width parameter.
2024-10-02 17:10:05 +02:00
644ef7e4e5
Merge pull request #2086 from VOGL-electronic/build_io_clocksignal
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build: io: don't use mutable object as default value
2024-10-01 11:49:03 +02:00
280b6b4ee4
build: io: don't use mutable object as default value
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don't use mutable object (here: ClockSignal()) as default value,
beacuse they will be the same object.
Leeds to problems, when for example two `SDRInput`
are used in two different Modules and one of them is
used with a `ClockDomainsRenamer()`, then both are changed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-30 15:18:11 +02:00
87ee6ec3a0
CHANGES.md: Prepare for post 2024.08 changes.
2024-09-27 09:58:09 +02:00
f72368abaa
CHANGES.md: Do 2024.08 release.
2024-09-27 09:45:11 +02:00
Gwenhael Goavec-Merou
enjoy-digital
Chris Keilbart
Gwenhael Goavec-Merou
Dolu1990
Fin Maaß
Andelf
Massimo Gaggero