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picorv32
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577 Commits 2 Branches 1 Tag 2.8 MiB
Commit Graph

146 Commits

Author SHA1 Message Date
Clifford Wolf 9d5f8ad8e6 Towards compressed ISA support 2015-11-19 04:02:00 +01:00
Clifford Wolf c4e711209c Towards compressed ISA support 2015-11-18 19:23:11 +01:00
Clifford Wolf 3aed9f7c65 Towards compressed ISA support 2015-11-18 15:55:29 +01:00
Clifford Wolf 8174d8fb7e Towards compressed ISA support 2015-11-15 23:24:38 +01:00
Clifford Wolf bfd2a4e0fa Towards compressed ISA support 2015-11-15 16:04:04 +01:00
Clifford Wolf bf4b0f3a63 Towards compressed ISA support 2015-11-14 19:22:00 +01:00
Clifford Wolf 60b9216856 Towards compressed ISA support 2015-11-14 14:11:21 +01:00
Clifford Wolf db26b51afe Towards compressed ISA support 2015-11-13 14:16:32 +01:00
Clifford Wolf 8eaeebf486 Progress in "make check" 2015-10-15 15:45:19 +02:00
Clifford Wolf 07f28068f6 Added "make check" 2015-10-14 23:26:04 +02:00
Clifford Wolf 16f97a86a1 Reset bugfix (bug found via scripts/smt2-bmc/mem_equiv.*) 2015-08-13 13:30:21 +02:00
Clifford Wolf bf7f984d42 Refactoring of TWO_CYCLE_ALU 2015-07-08 23:15:14 +02:00
Clifford Wolf dd30b57ea6 Added TWO_CYCLE_ALU parameter 2015-07-08 20:17:03 +02:00
Clifford Wolf b6c4c2eeb9 Added TWO_CYCLE_COMPARE 2015-07-07 22:51:52 +02:00
Clifford Wolf 9c028fc965 Added missing LD_RS1 debug statements 2015-07-02 14:51:28 +02:00
Clifford Wolf ab503d5756 Being more aggressive with parallel cases 2015-07-02 12:55:05 +02:00
Clifford Wolf c10125eb5c Added TWO_STAGE_SHIFT parameter 2015-07-02 12:29:06 +02:00
Clifford Wolf 853ce91300 Added `debug macro 2015-07-02 12:17:45 +02:00
Clifford Wolf c48a3b2434 Removed trailing whitespaces 2015-07-02 10:49:35 +02:00
Clifford Wolf 34193bf9df Added CATCH_MISALIGN and CATCH_ILLINSN 2015-07-01 21:20:51 +02:00
Clifford Wolf f6fe27ecbf After some profiling: one-hot FSM encoding 2015-07-01 21:20:31 +02:00
Clifford Wolf 4a9fda0737 Improvements in PCPI MUL core 2015-06-30 16:51:26 +02:00
Clifford Wolf 7417a3e249 Added LATCHED_IRQ parameter 2015-06-29 07:54:47 +02:00
Clifford Wolf 46026ba985 Added ENABLE_IRQ_QREGS and ENABLE_IRQ_TIMER 2015-06-28 22:09:51 +02:00
Clifford Wolf 21157b8f1d Cleanups in PCPI interface 2015-06-28 15:41:55 +02:00
Clifford Wolf b076d72806 Fixed PCPI instr prefetching 2015-06-28 14:51:53 +02:00
Clifford Wolf 1f99de5117 Improvements in picorv32_pcpi_mul 2015-06-28 13:07:50 +02:00
Clifford Wolf 4c15e05298 Moved ENABLE_MUL from picorv32_axi to picorv32 2015-06-28 12:19:49 +02:00
Clifford Wolf 034e1a6af7 Added PCPI to picorv32_axi 2015-06-27 23:54:11 +02:00
Clifford Wolf 7d1a484812 Implemented picorv32_pcpi_mul 2015-06-27 23:53:51 +02:00
Clifford Wolf dd8ed3c877 Added pcpi_wait interface 2015-06-26 23:48:50 +02:00
Clifford Wolf 0be990bd04 Added Pico Co-Processor Interface (PCPI) 2015-06-26 23:15:35 +02:00
Clifford Wolf 5d4ce82050 Implemented waitirq instruction 2015-06-26 10:39:08 +02:00
Clifford Wolf 9a4a06d981 Refactoring of IRQ handling 2015-06-26 10:03:37 +02:00
Clifford Wolf 23b700cf73 Added basic IRQ support 2015-06-25 14:08:39 +02:00
Clifford Wolf bb7f500489 Removed unnecessary "jal" complexity 2015-06-09 07:40:30 +02:00
Clifford Wolf a9532f81ed Refactored instruction decoder 2015-06-08 09:08:19 +02:00
Clifford Wolf 32208c0b70 Improved timing for "decoded_imm_uj" 2015-06-07 22:50:49 +02:00
Clifford Wolf 34d9dea8c7 Added support for dual-port register file 2015-06-07 20:53:19 +02:00
Clifford Wolf 60867e10a9 minor optimizations 2015-06-07 20:08:04 +02:00
Clifford Wolf 8e3e0bfba0 Improved "decoder_trigger" handling 2015-06-07 19:49:38 +02:00
Clifford Wolf bbbcea2faa Added look-ahead write interface 2015-06-07 12:11:20 +02:00
Clifford Wolf e84f044bc5 Major redesign of main FSM 2015-06-07 11:49:47 +02:00
Clifford Wolf bc8ffd2ecb Added memory "look-ahead" read interface 2015-06-06 20:50:53 +02:00
Clifford Wolf 7fd24a96b2 Improved AXI Interface Testbench 2015-06-06 17:15:09 +02:00
Clifford Wolf 77ba5a1897 Initial import 2015-06-06 14:14:32 +02:00