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1164 Commits

Author SHA1 Message Date
Dolu1990 49488d19af pipeline data cache unaligned access check 2020-09-07 12:01:11 +02:00
Dolu1990 775b336ee0
Merge pull request #136 from zeldin/rv32e 
Add support for RV32E in RegFilePlugin
 2020-09-06 22:23:24 +02:00
Marcus Comstedt 8e466dd13c Add support for RV32E in RegFilePlugin 
The RV32E extension removes registers x16-x31 from the ISA.  This
is useful when compiling with -mem2reg to save on BRAMs.  On iCE40
HX8K this option saves 1285 LC:s, which also improves the routing
situation, when using -mem2reg.

Note that the illegal instruction exception required by the RV32E
specification for accesses to registers x16-x31 is not implemented.
 2020-09-06 17:05:31 +02:00
Dolu1990 4c3cad97d3 fix CfuPlugin generation 2020-09-04 10:36:12 +02:00
Marcus Comstedt c489143442 Add support for big endian byte ordering 2020-08-30 15:17:09 +02:00
Dolu1990 7dcaa0c390 VexRiscvSmpCluster now avoid useless decoder for plic/clint 2020-08-13 11:26:11 +02:00
Dolu1990 69d5ba239a Smp config now initialise regfile using logic 2020-07-28 16:15:17 +02:00
Dolu1990 cc423cbe49 Litex cluster add DMA sel feature 2020-07-21 19:42:27 +02:00
Dolu1990 15bda15bc9 Litex cluster can now set cache layout 2020-07-21 19:35:56 +02:00
Dolu1990 9f62f37538 improve LitexCluster area for single core configuration 2020-07-21 15:45:02 +02:00
Dolu1990 da666ade49 Add VexRiscvLitexSmpClusterCmdGen 2020-07-21 15:07:32 +02:00
Dolu1990 fe5401f835 BmbGenerators refractoring (bus -> ctrl) 2020-07-16 13:04:25 +02:00
Dolu1990 da73317912 Cleanup BmbGenerators 2020-07-15 20:51:46 +02:00
Dolu1990 5f0aec7570 BmbInterconnectGenerator refractoring 2020-07-15 17:03:05 +02:00
Dolu1990 4f5ba6b044 Merge branch 'bmbRework' into dev 2020-07-10 13:06:20 +02:00
Dolu1990 f6931784a5 Merge branch 'smp' into dev 2020-07-10 13:00:50 +02:00
Dolu1990 d0a572de98 Add openroad config 2020-07-08 01:37:10 +02:00
Dolu1990 32f778613f DBusCachedPlugin now support asyncTagMemory 2020-07-08 01:36:58 +02:00
Dolu1990 60ee7e2b4c Better VexRiscvSmpCluster config 2020-07-08 01:36:40 +02:00
Dolu1990 51070d0e69 Fix MmuPlugin when used in multi stage config 2020-07-05 13:17:39 +02:00
Dolu1990 06584518da Remove CsrPlugin redoInterface combinatorial depedency from execut_isStuck 2020-07-05 13:17:07 +02:00
Dolu1990 a404078117 Few fixes 2020-07-05 13:16:39 +02:00
Dolu1990 c51e25f8c4 Litex SoC add coherent DMA master 2020-07-05 13:15:44 +02:00
Dolu1990 32539dfe6d Got VexRiscvSmpLitexCluster refractoring to work 2020-06-30 22:29:33 +02:00
Dolu1990 0da94ac66f Bring back smp cluster parameters 2020-06-29 15:49:01 +02:00
Dolu1990 062509deee Update Bmb brides and comment out SmpCluster for now 2020-06-29 11:44:10 +02:00
Dolu1990 c12f9a378d Fix inv regression 2020-06-20 13:18:46 +02:00
Dolu1990 f0f2cf61da D$ inv/ack are now fragment, which ease serialisation of wider invalidations 2020-06-19 15:57:56 +02:00
Dolu1990 c18bc12cb2 Fix DebugPlugin.fromBmb 2020-06-19 15:57:21 +02:00
Dolu1990 490c1f6b02 cleanup of old todo 2020-06-19 15:56:45 +02:00
Dolu1990 b0cd88c462 SmpCluster now with proper jtag and plic 2020-06-12 16:18:41 +02:00
Dolu1990 2e8a059c77 Fix travis verilator 2020-06-07 11:33:24 +02:00
Dolu1990 cb5597818d Fix d$ generation crash 2020-06-07 11:29:07 +02:00
Dolu1990 1f9fce6388 Fix d$ uncached writes exception handeling 2020-06-06 22:12:37 +02:00
Dolu1990 760d2f74d0 Update litex cluster to implement utime 2020-06-05 13:31:24 +02:00
Dolu1990 d6455817e7 smp cluster now have 2w*4KB of d$ , no more rdtime emulation 2020-06-05 10:43:03 +02:00
Dolu1990 71760ea372 CsrPlugin now support utime csr to avoid emulation 2020-06-05 10:43:03 +02:00
Dolu1990 3dafe8708b Cfu update 2020-06-05 10:43:03 +02:00
Dolu1990 0668046407 More smp cluster profiling 2020-06-05 10:40:51 +02:00
Dolu1990 97c2dc270c Fix typo 2020-06-04 10:11:30 +02:00
Dolu1990 89c13bedbd Fix litex smp cluster sim 2020-06-03 16:31:54 +02:00
Dolu1990 73f88e47cb Fix BmbToLitexDram coherency 2020-06-03 16:31:54 +02:00
Dolu1990 db50f04653 Add litexMpCluster 2020-06-03 16:31:54 +02:00
Dolu1990 08189ee907 DebugPlugin now support Bmb 2020-06-02 19:13:55 +02:00
Dolu1990 2942d0652a fix Briey verilator 2020-06-01 11:18:25 +02:00
Dolu1990 5e5c730959 Add LitexSmpDevCluster with per cpu dedicated litedram ports 2020-05-29 10:56:55 +02:00
Dolu1990 bc4a2c3747 Fix SmpCluster jtag 2020-05-27 14:19:37 +02:00
Dolu1990 18cce053a3 Improve SingleInstructionLimiterPlugin to also include fetch stages 2020-05-27 14:19:17 +02:00
Dolu1990 a64fd9cf3b Add CsrPlugin external hartid 
d$ rsp/sync now decrement pendings by signal amount
 2020-05-20 13:49:10 +02:00
Dolu1990 380afa3130 SpinalHDL 1.4.2 2020-05-20 13:45:52 +02:00