219 Commits

Author	SHA1	Message	Date
Charles Papon	c49373f3d1	Fix missing JAL, JALR encoding	2017-03-21 10:29:09 +01:00
Charles Papon	787682d4f6	Add comments ... Some refractoring	2017-03-20 14:49:49 +01:00
Charles Papon	ecf853f491	Add Static/Dynamic branch prediction	2017-03-20 12:37:20 +01:00
Charles Papon	d569242124	Add Static branch prediction in decode stage	2017-03-19 23:27:35 +01:00
Charles Papon	88dee6d2bc	Reduce area with reg[0] optimisation	2017-03-18 19:32:54 +01:00
Charles Papon	fc1bb7249a	Add trace option to regresion	2017-03-18 14:06:42 +01:00
Charles Papon	5e9da0f27a	Add self checked dhrystone test	2017-03-18 12:32:14 +01:00
Charles Papon	31db6511dc	Fix performance of removed instruction which halt were halting the pipeline	2017-03-18 10:51:55 +01:00
Charles Papon	20ca348707	Fix dCmd sent while the execute stage is removed ... Pass dhrystone benchmark without error !	2017-03-17 21:26:42 +01:00
Charles Papon	7517ac797d	Add MUL/DIV/REM support with plugins (pass Riscv-Tests)	2017-03-17 11:45:01 +01:00
Charles Papon	bf5bebda08	PcManager now drive PC asyncronously (use 1 cycle less in jump) ... Fix bypass logic when read/write r0 Disable REGFILE_WRITE_VALID in decod stage when r0 is written	2017-03-15 21:10:44 +01:00
Charles Papon	c6610ea454	Fix halt arbitrations	2017-03-15 17:14:58 +01:00
Charles Papon	11797fbb6e	Add sim performance print	2017-03-14 23:25:04 +01:00
Charles Papon	70d910e7d7	Load/Store pass Riscv-Tests	2017-03-14 23:00:24 +01:00
Charles Papon	7065ed5d93	All base instruction pass Riscv-Test (load/store not tested)	2017-03-14 20:13:35 +01:00
Charles Papon	ad6964f0bb	Classify tests ... Riscv-test integration wip	2017-03-14 00:42:48 +01:00
Charles Papon	df99a0d963	Better decoding	2017-03-13 18:30:37 +01:00
Charles Papon	e36c90af03	Add decoder bench	2017-03-13 16:17:57 +01:00
Charles Papon	9fc82c9736	Pass verilator simple literal, add, jump	2017-03-12 20:12:40 +01:00