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VexRiscv
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581 Commits 39 Branches 2 Tags 15 MiB
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219 Commits

Author SHA1 Message Date
Charles Papon edf1b4ed5a Cleaning, better jtag perf 2017-06-18 16:10:27 +02:00
Charles Papon 88a2c4a603 Cleaning/Add documentation 2017-06-15 13:44:21 +02:00
Charles Papon f8678698fc Briey improve AXI FMax 
Faster debugginPlugin regression
 2017-06-11 11:52:59 +02:00
Charles Papon cbc770deb3 Improve TCP sockets latency 2017-06-10 19:38:42 +02:00
Charles Papon 9b9d9e2582 Add Uart monitor in the briey testbench 2017-06-10 16:09:14 +02:00
Charles Papon 11a63491bd Add YAML feature to store CPU info 2017-06-09 16:06:18 +02:00
Charles Papon 4b9668c063 Remove speed factor overriding when Trace 2017-06-09 08:41:12 +02:00
Charles Papon f46ec583d6 Briey is now working with DataCache on FPGA 2017-06-07 23:02:34 +02:00
Dolu1990 8dcf5cf68a Add missing import in Briey testbench 2017-06-07 16:56:29 +02:00
Charles Papon 8da413dec3 Briey SoC is now working with openOCD TCP JTAG connection. (GDB OK) 
Add SDRAM Verilator model
 2017-06-07 04:19:35 +02:00
Charles Papon 1e18daecc0 Add ICache and DCache axi bridges functions 
Add StaticMemoryTranslationPlugin
 2017-06-01 17:54:56 +02:00
Charles Papon ac16558b6b Add haltItByOther 
Axi4, remove some pipelining
 2017-05-30 17:49:29 +02:00
Charles Papon 6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) 2017-05-29 21:17:14 +02:00
Charles Papon 213e154b40 Fix regression test debugPlugin bus 2017-05-28 17:41:09 +02:00
Charles Papon 8dddc7e334 GDB + openOCD successfully connect ! 2017-05-25 13:36:54 +02:00
Charles Papon 75f6b78daf OpenOCD successfuly connected to target 2017-05-24 23:53:31 +02:00
Charles Papon 1efed60307 Fix DebugPlugin 
Add DebugPlugin regression (PASS)
 2017-05-22 19:23:11 +02:00
Charles Papon cc875d1c0b Add TCP server socket to manage debug access from openOCD (as instance) 2017-05-22 00:42:19 +02:00
Charles Papon 5cda2632df Start implementing debugPlugin test infrastructures 2017-05-21 23:50:40 +02:00
Charles Papon 9995c5109d move tests 2017-05-21 16:53:48 +02:00
Charles Papon 736478ff1d CsrPlugin now catch illegal CSR access (wrong address + to low privilege level) 2017-05-09 00:40:44 +02:00
Charles Papon a51c27970b Add opcode for clean/invalidate the datacache 
Change mmu opcodes
 2017-05-07 16:02:55 +02:00
Charles Papon 4d6a6fbb02 Fix Instruction Data cache exceptions 
Pass all tests including CSR/FreeRTOS
 2017-05-07 12:51:47 +02:00
Charles Papon ca1bc9cf69 DataCache plugin now support all exceptions 2017-05-07 10:44:41 +02:00
Charles Papon 534a4c3494 mmu working for instruction and data bus (both tested) 2017-05-03 18:42:54 +02:00
Charles Papon 2ed33106d6 MMU pass simple regression ! 2017-04-29 19:58:17 +02:00
Charles Papon 010ba568f0 MMU implemented 
Datacached using MMU implemented
It compile, but nothing is tested
 2017-04-28 16:41:23 +02:00
Charles Papon ba2ca77114 Two stage datacache now pass dhrystone benchmark without error 2017-04-23 23:15:38 +02:00
Charles Papon 9040326273 WIP two stage DCache, nearly passed the dhrystone benchmark 2017-04-23 18:31:16 +02:00
Charles Papon 024e14ae58 Smaller and faster single stage instruction cache 
Add fast two stage instruction cache
Remove useless address == 0 checks in the HazardPlugin
 2017-04-13 18:27:03 +02:00
Charles Papon c83a157c64 IBusCachedPlugin with twoStage config is now compatible with syncronous regfile 2017-04-09 11:59:09 +02:00
Charles Papon e3b9e671ec IBusCachedPlugin add two stage cache option for better FMax and better scaling 2017-04-08 17:42:13 +02:00
Charles Papon efb27390a7 Better IntAluPlugin 
Better SrcPlugin
Better DBusCachedPlugin
 2017-04-06 01:28:52 +02:00
Charles Papon 179e7f7b4c IBusCachedPlugin add asyncTagMemory option 2017-04-05 14:25:11 +02:00
Charles Papon 2b24cbc8e1 Add pessimistic harzard options 
Add separated add/sum option in srcPlugin
 2017-04-04 00:25:39 +02:00
Charles Papon 8ff05bd2a8 Much better decoder using Quine-Mc Cluskey 2017-04-02 21:05:25 +02:00
Charles Papon a9f7177181 Data cache pass dhrystone benchmark. 
Data cache todo -> bus error handling
 2017-04-01 17:06:59 +02:00
Charles Papon 2f384364d8 Data cache WIP 
refractoring
 2017-03-31 15:20:51 +02:00
Charles Papon 19fe998a52 Instruction cache is now able to catch bus errors 2017-03-30 17:34:24 +02:00
Charles Papon 95585b4d9a Add instruction cache plugin (tested) 2017-03-30 10:03:53 +02:00
Charles Papon 32d32845bd Add tests for iRsp, dRsp access faults 2017-03-28 20:25:58 +02:00
Charles Papon 62a55c4cf4 Add IRsp/dRsp ready + error capabilities to stall the bus and to generate access error exceptions 2017-03-28 01:24:29 +02:00
Charles Papon eecc1e6b18 Add MachineCsr.mbadaddr logics 2017-03-27 18:35:27 +02:00
Charles Papon 91c52f4e46 Decoder now catch illegal instructions 2017-03-26 18:02:48 +02:00
Charles Papon c5520656e5 Now able to catch missaligned instruction/data addresses 
Modify arbitration with an flushAll + isFlushed
 2017-03-26 17:20:07 +02:00
Charles Papon 4000191966 FreeRTOS tested 
removeIt no more colapse bubbles
 2017-03-25 16:44:42 +01:00
Charles Papon 9bbf3ee3e7 MachineCsr fix csr set/clear with zero 
MachineCsr pass external/timer interrupts test
 2017-03-24 17:40:37 +01:00
Charles Papon 72d65841d2 MachineCsr pass simple interrupt and exception tests 2017-03-23 23:12:44 +01:00
Charles Papon 94770f8e0b Add MachineCsr (untested) 2017-03-22 18:29:34 +01:00
Charles Papon e9d3977737 Add Arbitration.flushIt 
Add ExceptionService
Add unremovableStage
Add MachineCsr (untested)
 2017-03-21 18:40:50 +01:00
Charles Papon c49373f3d1 Fix missing JAL, JALR encoding 2017-03-21 10:29:09 +01:00
Charles Papon 787682d4f6 Add comments 
Some refractoring
 2017-03-20 14:49:49 +01:00
Charles Papon ecf853f491 Add Static/Dynamic branch prediction 2017-03-20 12:37:20 +01:00
Charles Papon d569242124 Add Static branch prediction in decode stage 2017-03-19 23:27:35 +01:00
Charles Papon 88dee6d2bc Reduce area with reg[0] optimisation 2017-03-18 19:32:54 +01:00
Charles Papon fc1bb7249a Add trace option to regresion 2017-03-18 14:06:42 +01:00
Charles Papon 5e9da0f27a Add self checked dhrystone test 2017-03-18 12:32:14 +01:00
Charles Papon 31db6511dc Fix performance of removed instruction which halt were halting the pipeline 2017-03-18 10:51:55 +01:00
Charles Papon 20ca348707 Fix dCmd sent while the execute stage is removed 
Pass dhrystone benchmark without error !
 2017-03-17 21:26:42 +01:00
Charles Papon 7517ac797d Add MUL/DIV/REM support with plugins (pass Riscv-Tests) 2017-03-17 11:45:01 +01:00
Charles Papon bf5bebda08 PcManager now drive PC asyncronously (use 1 cycle less in jump) 
Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
 2017-03-15 21:10:44 +01:00
Charles Papon c6610ea454 Fix halt arbitrations 2017-03-15 17:14:58 +01:00
Charles Papon 11797fbb6e Add sim performance print 2017-03-14 23:25:04 +01:00
Charles Papon 70d910e7d7 Load/Store pass Riscv-Tests 2017-03-14 23:00:24 +01:00
Charles Papon 7065ed5d93 All base instruction pass Riscv-Test (load/store not tested) 2017-03-14 20:13:35 +01:00
Charles Papon ad6964f0bb Classify tests 
Riscv-test integration wip
 2017-03-14 00:42:48 +01:00
Charles Papon df99a0d963 Better decoding 2017-03-13 18:30:37 +01:00
Charles Papon e36c90af03 Add decoder bench 2017-03-13 16:17:57 +01:00
Charles Papon 9fc82c9736 Pass verilator simple literal, add, jump 2017-03-12 20:12:40 +01:00