Commit Graph

219 Commits

Author SHA1 Message Date
Dolu1990 9d55283b3b Machine mode emulator 2019-03-25 02:00:19 +01:00
Dolu1990 e28702eb40 Add PlicCost test 2019-03-24 12:17:39 +01:00
Dolu1990 6c0608f0dd #60
Add LitexSoC workspace / linux loading.
Need to emulate peripherals and adapte the kernel now.
Probably also need some machine mode emulation
Software time !
2019-03-24 10:52:56 +01:00
Dolu1990 0656a49332 Make xtval more compliant 2019-03-23 20:12:36 +01:00
Dolu1990 7159237104 Fix csrrs/csrrc for xip registers 2019-03-23 18:11:26 +01:00
Dolu1990 505bff6f45 CSR Plugin now implement interruptions as specified in the spec 2019-03-23 12:56:04 +01:00
Dolu1990 3652ede130 Add mdeleg tests 2019-03-23 11:41:10 +01:00
Dolu1990 9139b4d269 Restore all tests 2019-03-22 18:03:35 +01:00
Dolu1990 597336b491 MMU sum/mxr tested and ok, all seem finen 2019-03-22 17:11:55 +01:00
Dolu1990 f7b793b7bf Add SSTATUS.SUM/MXR feature, need testing 2019-03-22 15:49:36 +01:00
Dolu1990 e4cdc2397a MMU pass all test, need to and SUM and MXR and it's all ok 2019-03-22 14:52:49 +01:00
Dolu1990 2b458fc642 Added MMU superpage support, pass MMU tests 2019-03-22 12:23:47 +01:00
Dolu1990 af2acbd46e Got the new MMU design to pass simple tests #60 2019-03-22 01:10:17 +01:00
Dolu1990 ea56481ead Add supervisor CSR in the riscv golden model 2019-03-20 23:26:08 +01:00
Dolu1990 6f2e5a0eb7 goldenmodel Implement some of the supervisor CSR 2019-03-20 20:28:04 +01:00
Dolu1990 d205f88fb8 riscv golden model and RTL pass all current regressions
add RVC into the linux config
2019-03-20 12:17:43 +01:00
Dolu1990 3c66f7c58a goldenmodel now pass more machine mode CSR tests 2019-03-20 11:46:27 +01:00
Dolu1990 ee402ec5dc clearning 2019-03-20 01:16:39 +01:00
Dolu1990 3a38fe4130 Add mmu regresion blank project 2019-03-20 01:13:05 +01:00
Dolu1990 ccc3b63d7c Enable golden model check for all regressions
Need to implement missing CSR of the golden model
2019-03-20 01:12:03 +01:00
Dolu1990 3fbc2f4458 Fix generation 2019-03-19 20:29:28 +01:00
Dolu1990 f4598fbd0a Add tightly coupled interface to the i$ 2019-01-21 23:46:18 +01:00
Dolu1990 d9029c2efc Fix #46 by filling missing return statements 2018-12-10 01:44:47 +01:00
Dolu1990 281d61bbe1 regression fix hex << dec #46 2018-12-09 16:37:16 +01:00
Dolu1990 1fbb81a4d9 regression fix delete [] #46 2018-12-09 15:40:02 +01:00
Dolu1990 f121ce1ed5 add sanity asserts in regression #46 2018-12-08 14:10:18 +01:00
Dolu1990 9330945623 fix regression makefile 2018-12-07 23:50:13 +01:00
Dolu1990 52419fd7ad Regression remove dplus stuff #46 2018-12-07 23:47:49 +01:00
Dolu1990 68fdbe60cc verilator regression fix missing fclose #46 2018-12-07 23:43:19 +01:00
Dolu1990 ac1ed40b80 Move things into SpinalHDL lib 2018-12-01 18:25:18 +01:00
Dolu1990 2f6a2dfccc Add configs setup in SimpleBusInterconnect 2018-11-29 16:14:45 +01:00
Dolu1990 0d92a5e5cd Add many little options to reduce area 2018-11-12 14:14:34 +01:00
Dolu1990 905abd5aaa Add wfiGenAsWait and wfiGenAsNop
CsrPlugin cleaning
Much cleaning in general
Zephyr is running
2018-10-16 13:07:30 +02:00
Dolu1990 f903df4b66 sync 2018-10-12 17:13:54 +02:00
Dolu1990 0b8f6f6ed4 Fix broken C.LWSP reference_output 2018-10-12 12:02:02 +02:00
Dolu1990 594f7a8bf2 Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test 2018-10-11 22:19:17 +02:00
Dolu1990 c26b7e15cf BranchPlugin exceptions are now risc-v compliance alligned 2018-10-11 17:56:49 +02:00
Dolu1990 8b1a4a2717 Add RISCV compliance regression test, need to fix I-MISALIGN_JMP-01 mtval 2018-10-11 00:25:39 +02:00
Dolu1990 0662cc2797 Add GenMicro experiment to reduce ice40 area usage.
IBusSimplePlugin now require cmdFork parameters to be set (no default)
2018-10-03 22:08:57 +02:00
Dolu1990 48bff80653 rework fetchPc to optionaly share the pcReg with the stage(1)
IBusSimplePlugin now implement cmdForkPersistence option
2018-10-03 16:24:10 +02:00
Dolu1990 c61f17aea3 Fetcher/IBusSimplePlugin wip 2018-10-03 01:02:22 +02:00
Dolu1990 0ada869b2d regression golden ref regfile is now sync with trl boot's random values
wip
2018-10-01 16:14:21 +02:00
Dolu1990 7770eefa3b wip 2018-09-30 12:57:08 +02:00
Dolu1990 aff436ddcf Sync with SpinalHDL head
Add mmu test into the dhrystone regression command
2018-09-24 18:31:33 +02:00
Dolu1990 1e3b75ef1d xip typo 2018-09-23 22:06:21 +02:00
Dolu1990 86efb75f6a rework fetcher 2018-09-23 22:05:53 +02:00
Dolu1990 ff1d1072a7 XIP is physicaly working on murax 2018-09-19 00:09:14 +02:00
Dolu1990 b51ac03a5e murax xip flash integration wip 2018-09-18 16:53:26 +02:00
Dolu1990 d7cba38ec2 move to SpinalHDL 1.1.7, add more default value for plugins parameters 2018-09-11 16:08:28 +02:00
Dolu1990 791608f655 Move swing stuff into main test package 2018-08-29 14:55:25 +02:00