Dolu1990
|
0255f51cc5
|
Add unpipelined Wishbone support for uncached version
|
2018-08-24 16:41:34 +02:00 |
|
Dolu1990
|
7ed6835e97
|
Add C++ VexRiscv model to cross check the hardware simulation
|
2018-08-22 02:08:55 +02:00 |
|
Dolu1990
|
38af5dbdd5
|
riscv emulator WIP (RVC missing)
|
2018-08-21 01:03:51 +02:00 |
|
Dolu1990
|
8ebb3af4fc
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
Conflicts:
README.md
src/main/scala/vexriscv/TestsWorkspace.scala
src/test/scala/vexriscv/Play.scala
|
2018-08-17 20:56:51 +02:00 |
|
Dolu1990
|
1d3ac7830b
|
restore tests without CSR catch all
|
2018-08-17 19:33:41 +02:00 |
|
Dolu1990
|
330ee14a23
|
final fetchRework commit ?
|
2018-08-17 19:13:23 +02:00 |
|
Dolu1990
|
91773ec7d5
|
Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue
|
2018-08-14 11:51:53 +02:00 |
|
Dolu1990
|
32fe1dcbd4
|
Add google cloud VM regressions scripts
|
2018-07-07 21:47:09 +02:00 |
|
Dolu1990
|
3ea4f28354
|
wip
|
2018-07-07 11:39:42 +02:00 |
|
Dolu1990
|
9c1a8ea219
|
Fix EPC
Fix Freertos binaries
wip
|
2018-07-03 23:17:32 +02:00 |
|
Dolu1990
|
ffe5fa23f0
|
wip
|
2018-06-25 09:36:07 +02:00 |
|
Dolu1990
|
d73aa9ce00
|
rework csr exception/interrupt handeling wip
|
2018-06-24 00:14:55 +02:00 |
|
Dolu1990
|
8886f7e6d4
|
test wip
|
2018-06-19 16:15:42 +02:00 |
|
Dolu1990
|
1090111a6f
|
TestIndividual is now fully random
|
2018-06-15 13:00:59 +02:00 |
|
Dolu1990
|
83864710a3
|
Fix IBusCached single cycle interaction with mmu bus
Add random test configs
|
2018-06-09 08:40:19 +02:00 |
|
Dolu1990
|
08a1212fca
|
Add DBus simple/cached regressions
|
2018-06-07 02:31:18 +02:00 |
|
Dolu1990
|
6bc5431fcd
|
Add iBusCached regressions
|
2018-06-07 00:57:26 +02:00 |
|
Dolu1990
|
5e7dd02bf7
|
Fix relaxedPc/DYNAMIC_TARGET interaction
|
2018-06-06 18:30:30 +02:00 |
|
Dolu1990
|
7768f065e4
|
Add many cpu configs on regressions tests (some config are broken)
|
2018-06-06 02:23:07 +02:00 |
|
Dolu1990
|
930563291c
|
Allow RVC/dynamic_target/fetch bus latency > 1 all together
Fix freeretos rvc regressions
|
2018-06-05 02:21:05 +02:00 |
Tom Verbeure
|
52f1cdbca7
|
Fix some missing Barriel -> barriel fixes
|
2018-06-03 21:46:40 -07:00 |
|
Dolu1990
|
9f0387350b
|
Add Freertos RVC binaries regression
|
2018-06-03 17:10:58 +02:00 |
|
Dolu1990
|
7375855e58
|
DYNAMIC_PREDICTION used with RVC pass tests (1 cycle fetch)
|
2018-06-03 00:50:18 +02:00 |
|
Dolu1990
|
5943ee727e
|
Fill travis, DhrystoneBench is now a Unit test
|
2018-05-28 09:02:01 +02:00 |
|
Dolu1990
|
9815763b7f
|
Merge remote-tracking branch 'origin/master' into reworkFetcher
Conflicts:
src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala
src/test/cpp/regression/main.cpp
|
2018-05-24 14:04:01 +02:00 |
|
Dolu1990
|
2f8ccc55b6
|
Fix branch plugin decode prediction exception by using the instruction decoder
|
2018-05-24 12:52:00 +02:00 |
|
Dolu1990
|
a53f8fdc35
|
Clean configs
|
2018-05-23 16:57:32 +02:00 |
|
Dolu1990
|
acccbf40e2
|
RVC debug pass tets
|
2018-05-09 00:28:14 +02:00 |
|
Dolu1990
|
0056da1342
|
DebugPlugin work
|
2018-05-08 02:01:34 +02:00 |
|
Dolu1990
|
a50fbf0d7a
|
Fix IBusCachedPlugin Pass all dhrystone tests
|
2018-04-30 13:35:17 +02:00 |
|
Dolu1990
|
6598e82920
|
wishbone => word address, not byte address
|
2018-04-19 11:22:06 +02:00 |
|
Dolu1990
|
455607b6b4
|
Fix dBus IO access
|
2018-04-18 14:11:59 +02:00 |
|
Dolu1990
|
6e59ddcc73
|
Cached wishbone demo is passing regression tests
|
2018-04-18 13:51:33 +02:00 |
|
Dolu1990
|
76352b44fa
|
wip
|
2018-04-13 12:51:27 +02:00 |
|
Dolu1990
|
c48c7170e8
|
Added many pipelining option into IBusSimplePlugin
|
2018-03-23 19:07:03 +01:00 |
|
Dolu1990
|
351ad10925
|
RVC Add dhrystone regressions (PASS)
|
2018-03-21 23:36:57 +01:00 |
|
Dolu1990
|
0c7c2a1fba
|
IBusPlugin add support of bus error when using compressed instruction
|
2018-03-21 22:34:54 +01:00 |
|
Dolu1990
|
31a464ffdc
|
VexRiscv now pass Riscv-test compressed stuff
|
2018-03-21 20:50:07 +01:00 |
|
Dolu1990
|
af638e7bde
|
RV32IC is passing some of the compressed Riscv-test tests
|
2018-03-21 20:30:09 +01:00 |
|
Dolu1990
|
1fb138de1f
|
IBusSimplePlugin fully functional Need to restore branch prediction
|
2018-03-20 00:01:28 +01:00 |
|
Dolu1990
|
ac74fb9ce8
|
iBusSimplePlugin done, DebugPlugin need minor rework
|
2018-03-18 13:21:21 +01:00 |
|
Dolu1990
|
5228a53293
|
MuraxSim improve simulation Speed
|
2018-03-06 12:20:39 +01:00 |
|
Dolu1990
|
9b2cd7b234
|
MuraxSim add switch
|
2018-03-06 12:17:15 +01:00 |
|
Dolu1990
|
5260ad5c35
|
Decoding lib cleaning
|
2018-02-25 08:57:31 +01:00 |
|
Dolu1990
|
137b1ee32c
|
Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values
|
2018-02-22 22:36:13 +01:00 |
|
Dolu1990
|
d0e963559a
|
Update readme with the new ICache implementation
|
2018-02-18 23:48:11 +01:00 |
|
Dolu1990
|
93110d3b95
|
Add jump priority managment in PcPlugins
|
2018-02-16 14:27:20 +01:00 |
|
Dolu1990
|
506e0e3f60
|
New faster/smaller/multi way instruction cache design.
Single or dual stage
|
2018-02-16 02:21:08 +01:00 |
|
Dolu1990
|
3ee111e100
|
Update readme (gcc stuff)
|
2018-02-05 16:34:10 +01:00 |
|
Dolu1990
|
d4b05ea365
|
Remap Briey/Murax onChipRam to 0x80000000 to avoid having memory at the null pointer location
Commit missing file
Update dhrystone hex to use GP. 1.44 DMIPS/Mhz
|
2018-02-05 16:16:27 +01:00 |
|
Dolu1990
|
b7d8ed8a81
|
Add onWrite/onRead/isWriting/isReading on the CsrPlugin
|
2018-02-01 21:28:28 +01:00 |
|
Dolu1990
|
4ee2482cbf
|
Fix custom_csr regression against random ibus stall
|
2018-01-31 18:33:21 +01:00 |
|
Dolu1990
|
30b05eaf96
|
Add CsrInterface to allow custom CSR addition
Add CustomCsrDemoPlugin as a show case
|
2018-01-31 18:13:42 +01:00 |
|
Dolu1990
|
bdbf6ecf17
|
BranchPrediction DYNAMIC_TARGET add source PC tag to only consume entries on branch instructions
|
2018-01-29 14:52:31 +01:00 |
|
Dolu1990
|
0d318ab6b9
|
Add DYNAMIC_TARGET branch prediction (1.41 DMIPS/Mhz)
Add longer timeouts in the regressions tests
|
2018-01-29 13:17:11 +01:00 |
|
Dolu1990
|
93da5d29bc
|
Fix dhrystone referance log
|
2018-01-28 16:34:55 +01:00 |
|
Dolu1990
|
26732942e5
|
Update DMIPS/Mhz
Add cached config with maximal performance settings
FullBarrielShifterPlugin can now be configured to do everything in the execute stage
|
2018-01-25 01:11:57 +01:00 |
|
Dolu1990
|
3b3bbd48b9
|
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
|
2018-01-20 18:29:33 +01:00 |
|
Dolu1990
|
6a521a8d13
|
Better MuraxSim gui
Add MuraxSim in the readme
|
2018-01-09 08:59:17 +01:00 |
|
Dolu1990
|
43d3ffd685
|
CsrPlugin : Now wait that the whole pipeline (including writeback) is empty before executing interruptions. This make the separation between context switching clear and avoid on atomic instructions failure
|
2018-01-04 17:37:23 +01:00 |
|
Dolu1990
|
2b7465e5df
|
Add more atomic tests (PASS)
|
2018-01-04 16:16:22 +01:00 |
|
Dolu1990
|
611f2f487f
|
Fix DataCache atomic integration into DBusCachedPlugin
Atomic is passing basic tests
|
2018-01-04 15:24:00 +01:00 |
|
Dolu1990
|
4637e6cb48
|
Fix DecodingSimplePlugin model building when reinvocation is done one a preexisting opcode.
add Atomic test flow
|
2018-01-04 14:43:30 +01:00 |
|
Dolu1990
|
468dd3841e
|
Add Atomic LR SC support to the DBusCachedPlugin via reservation entries buffer
|
2018-01-04 13:16:40 +01:00 |
|
Dolu1990
|
4ed19f2cc5
|
SpinalHDL 1.1.1
|
2017-12-30 03:36:57 +01:00 |
|
Dolu1990
|
0d39e38906
|
SpinalHDL 1.1.0
|
2017-12-28 13:49:39 +01:00 |
|
Dolu1990
|
3c0588eb4b
|
remove MuraxSim fixed path
|
2017-12-19 22:33:46 +01:00 |
|
Dolu1990
|
7f2b2181c1
|
SpinalHDL 1.0.3
|
2017-12-19 21:21:16 +01:00 |
|
Dolu1990
|
37849b7a66
|
Spinal 1.0.2 sim update
|
2017-12-19 00:40:52 +01:00 |
|
Dolu1990
|
ebda7526b5
|
MuraxSim 1.0.0
|
2017-12-17 17:57:09 +01:00 |
|
Dolu1990
|
dda5372a6c
|
Fix typo
|
2017-12-14 01:05:06 +01:00 |
|
Dolu1990
|
d6e0761065
|
Fix led gui refresh rate
|
2017-12-14 01:04:31 +01:00 |
|
Dolu1990
|
2259c9cb0f
|
Add SpinalHDL sim (1.0.0)
|
2017-12-14 00:57:12 +01:00 |
|
Dolu1990
|
b7f4f09814
|
Update verilator makefiles to support the last SpinalHDL changes (process merges)
|
2017-11-21 23:56:46 +01:00 |
Ubuntu
|
008a5b7309
|
updated main.cpp
added missing using namespace std
|
2017-10-17 22:09:08 +00:00 |
Dolu1990
|
aa859aae6b
|
Update framework.h
Add missing using namespace std;
|
2017-10-05 10:08:09 +02:00 |
|
Dolu1990
|
8168c9bf3a
|
Update simd_add makefile
|
2017-08-27 14:49:36 +02:00 |
|
Charles Papon
|
54b06e6438
|
Add SIMD_ADD regression and config (show case)
|
2017-08-08 18:19:02 +02:00 |
|
Charles Papon
|
f44b345132
|
Add console TX in the Murax verilator
|
2017-07-31 21:04:41 +02:00 |
|
Charles Papon
|
c16a53c388
|
Refractoring of some arbitration signals
Add UART into Murax
|
2017-07-31 13:34:25 +02:00 |
|
Charles Papon
|
e8aa828744
|
PcPlugin change fastPcCalculation into relaxedPcCalculation
relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
|
2017-07-29 21:36:30 +02:00 |
|
Charles Papon
|
3b66d986a8
|
Fix cpu sending instruction memory request while being halted by the DebugPlugin
|
2017-07-29 18:20:22 +02:00 |
|
Charles Papon
|
fa887d3830
|
Add pipelining option (hit 60 Mhz)
|
2017-07-29 02:52:03 +02:00 |
|
Charles Papon
|
823ac353ff
|
Add Murax SoC (very light, work on ice40)
|
2017-07-28 21:25:49 +02:00 |
|
Charles Papon
|
493f7721cb
|
All FreeRTOS tests are now passing
|
2017-07-28 00:07:51 +02:00 |
|
Charles Papon
|
800e9e79a5
|
freertos regression now include O0 and O3 for rv32i and rv32im
|
2017-07-27 01:23:50 +02:00 |
|
Charles Papon
|
6b3e2dbe7d
|
Add FreeRTOS test regression (FREERTOS=yes)
Multithreaded regression
|
2017-07-26 23:38:59 +02:00 |
|
Charles Papon
|
6d117f5c81
|
Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages)
freeRTOS pass
|
2017-07-23 22:58:26 +02:00 |
|
Charles Papon
|
4b5bf7d807
|
Briey Area down by 10% by spliting the memory system in two (System, Debug)
|
2017-07-23 01:11:33 +02:00 |
|
Charles Papon
|
37c338ec98
|
Avalon add read response support.
Fix debug instruction injection and IBusSimplePlugin interraction
|
2017-07-21 20:39:54 +02:00 |
|
Charles Papon
|
54f785b1a3
|
Add full avalon support (pass regression)
|
2017-07-21 17:40:45 +02:00 |
|
Charles Papon
|
52f5020e64
|
Rename some regression commands
Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
|
2017-07-21 14:32:49 +02:00 |
|
Charles Papon
|
575a410786
|
Avalon regression (WIP)
|
2017-07-20 14:20:19 +02:00 |
|
Charles Papon
|
fcec6cba86
|
revert test changes
|
2017-07-17 15:26:37 +02:00 |
|
Charles Papon
|
617861ee6c
|
Add smallAndProductive
|
2017-07-17 15:25:56 +02:00 |
|
Charles Papon
|
bc792a8655
|
Fix UartRx sim
|
2017-07-15 19:05:34 +02:00 |
|
Charles Papon
|
d3dcfcec06
|
Add toAvalon bridge to cached bus
Add VexRiscvAvalon demo
|
2017-07-14 18:04:41 +02:00 |
|
Charles Papon
|
f51f28164a
|
Fix info to flush data cache
Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
|
2017-07-09 01:00:46 +02:00 |
|
Charles Papon
|
e9ab3d71d5
|
update readme
add uart.elf binary for testing
|
2017-06-26 14:44:52 +02:00 |
|
Charles Papon
|
e9e7cf9e7a
|
Add briey tracing
Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
|
2017-06-24 14:09:12 +02:00 |