e8aa828744
PcPlugin change fastPcCalculation into relaxedPcCalculation
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relaxedPcCalculation relax timings on the IBusSimple address => better FMax when the CPU is integrated into a SoC
2017-07-29 21:36:30 +02:00
3b66d986a8
Fix cpu sending instruction memory request while being halted by the DebugPlugin
2017-07-29 18:20:22 +02:00
43253f61c1
Update Murax info
2017-07-29 02:52:57 +02:00
fa887d3830
Add pipelining option (hit 60 Mhz)
2017-07-29 02:52:03 +02:00
3bdf020c67
Add interrupts and timer to Murax
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8KB ram is the default now
2017-07-29 01:59:17 +02:00
823ac353ff
Add Murax SoC (very light, work on ice40)
2017-07-28 21:25:49 +02:00
1450077b70
Add Murax SoC (wip)
2017-07-28 14:16:30 +02:00
493f7721cb
All FreeRTOS tests are now passing
2017-07-28 00:07:51 +02:00
800e9e79a5
freertos regression now include O0 and O3 for rv32i and rv32im
2017-07-27 01:23:50 +02:00
6b3e2dbe7d
Add FreeRTOS test regression (FREERTOS=yes)
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Multithreaded regression
2017-07-26 23:38:59 +02:00
10d282b2ef
Add DBusSimple early injection feature (better DMIPS)
2017-07-26 23:36:25 +02:00
6d117f5c81
Fix DataCache bug (interaction between the victim buffer and the memory read request in execute/memory stages)
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freeRTOS pass
2017-07-23 22:58:26 +02:00
9fe4e1d54d
Package refractoring VexRiscv -> vexriscv Plugin -> plugin
2017-07-23 13:28:17 +02:00
4b5bf7d807
Briey Area down by 10% by spliting the memory system in two (System, Debug)
2017-07-23 01:11:33 +02:00
37c338ec98
Avalon add read response support.
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Fix debug instruction injection and IBusSimplePlugin interraction
2017-07-21 20:39:54 +02:00
54f785b1a3
Add full avalon support (pass regression)
2017-07-21 17:40:45 +02:00
52f5020e64
Rename some regression commands
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Add Avalon regressions (PASS)
DebugModule read response is now 1 cycle latency
2017-07-21 14:32:49 +02:00
575a410786
Avalon regression (WIP)
2017-07-20 14:20:19 +02:00
570f0e1e3e
D$ remove the coupling between the mem.cmd.ready >> victim logic >> cpu halt by using halfPipe => Better practical FMax
2017-07-20 14:20:19 +02:00
8643086fc0
Add Briey area and timings into readme
2017-07-19 18:34:16 +02:00
42e546ecd9
Add fullNoMmuNoCache config
2017-07-17 16:45:06 +02:00
fcec6cba86
revert test changes
2017-07-17 15:26:37 +02:00
617861ee6c
Add smallAndProductive
2017-07-17 15:25:56 +02:00
99c3397243
readme, better plugin example
2017-07-17 14:19:28 +02:00
84bba3adf0
REG1/REG2 refractoring RS1/RS2
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Add CustomeInstruction example
2017-07-17 14:02:56 +02:00
708a8f66de
typo fixes
2017-07-17 14:01:35 +02:00
79c2972076
Update bench config with realistic embedded CSR
2017-07-16 14:34:42 +02:00
53300c4116
Add area and FMax in readme
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Add Synthesis bench
2017-07-16 13:50:19 +02:00
37ea699c55
Add Synthesis bench
2017-07-16 03:29:50 +02:00
6930e76042
Remove mepc from smallest CSR config
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Better readme
2017-07-16 00:44:23 +02:00
bc792a8655
Fix UartRx sim
2017-07-15 19:05:34 +02:00
74becb6633
Add VexRiscvAvalon QSysify
2017-07-15 09:41:39 +02:00
12d21a08e8
Add DebugPlugin avalon
2017-07-14 19:28:22 +02:00
d3dcfcec06
Add toAvalon bridge to cached bus
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Add VexRiscvAvalon demo
2017-07-14 18:04:41 +02:00
f51f28164a
Fix info to flush data cache
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Briey sim add VGA GUI (SDL2)
Add DE0-Nano Briey support
2017-07-09 01:00:46 +02:00
8d34c04425
Fix CsrPlugin case issue
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Better DBusSimplePlugin FMax with catch enables
SrcPlugin can now insert SRC1 and SRC2 in the execute mode for lower area usage and combinatorial path balancing
2017-06-27 19:37:46 +02:00
e9ab3d71d5
update readme
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add uart.elf binary for testing
2017-06-26 14:44:52 +02:00
4d7455f9c3
add retiming to the dataCache waysHit
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Add exception catches in the default briey configuration
2017-06-26 14:02:25 +02:00
e9e7cf9e7a
Add briey tracing
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Better debugPlugin implementation
Fix SimpleDBus/IBus into AXI bridge (cmd transaction removing)
Add SingleInstructionLimiterPlugin for debug purposes
2017-06-24 14:09:12 +02:00
edf1b4ed5a
Cleaning, better jtag perf
2017-06-18 16:10:27 +02:00
bc90331c49
Cleaning
2017-06-15 13:54:34 +02:00
88a2c4a603
Cleaning/Add documentation
2017-06-15 13:44:21 +02:00
835dd4ad50
Add CSR
2017-06-15 11:16:11 +02:00
f8678698fc
Briey improve AXI FMax
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Faster debugginPlugin regression
2017-06-11 11:52:59 +02:00
cbc770deb3
Improve TCP sockets latency
2017-06-10 19:38:42 +02:00
9b9d9e2582
Add Uart monitor in the briey testbench
2017-06-10 16:09:14 +02:00
11a63491bd
Add YAML feature to store CPU info
2017-06-09 16:06:18 +02:00
4b9668c063
Remove speed factor overriding when Trace
2017-06-09 08:41:12 +02:00
f46ec583d6
Briey is now working with DataCache on FPGA
2017-06-07 23:02:34 +02:00
8dcf5cf68a
Add missing import in Briey testbench
2017-06-07 16:56:29 +02:00
Charles Papon