Commit Graph

345 Commits

Author SHA1 Message Date
Dolu1990 2f8ccc55b6 Fix branch plugin decode prediction exception by using the instruction decoder 2018-05-24 12:52:00 +02:00
Dolu1990 a53f8fdc35 Clean configs 2018-05-23 16:57:32 +02:00
Dolu1990 eb5bc4a791 Fix RVC decompressor (ALU immediats) 2018-05-22 17:23:20 +02:00
Dolu1990 ff760a0bf0 DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS) 2018-05-21 13:45:08 +02:00
Dolu1990 7ffbfab312 Reintroduce MMU feature (pass tests) 2018-05-16 20:32:12 +02:00
Dolu1990 35fbf177e2 Update to SpinalHDL 1.1.6 2018-05-16 12:12:09 +02:00
Dolu1990 c8cec59f1d Update IBusCachedPlugin parameters 2018-05-16 12:11:53 +02:00
Dolu1990 3b54ecf303 Restore two cycle instruction cache features 2018-05-15 23:03:33 +02:00
Dolu1990 df3d9ccb13 rework IBusSimplePlugin parameters 2018-05-14 10:31:40 +02:00
Dolu1990 c0271d382f More assertion (csrPlugin) 2018-05-14 10:13:44 +02:00
Dolu1990 9caa7163ae IBusSimplePlugin add relaxedBusCmdValid feature 2018-05-14 10:04:19 +02:00
Dolu1990 610bd01f3b remove rspStageGen 2018-05-14 09:21:28 +02:00
Dolu1990 7b37669a0f Add exception catch to iBusSimplePLugin (pass) 2018-05-09 18:43:48 +02:00
Dolu1990 acccbf40e2 RVC debug pass tets 2018-05-09 00:28:14 +02:00
Dolu1990 0056da1342 DebugPlugin work 2018-05-08 02:01:34 +02:00
Dolu1990 e65757e34c wip before moving the fetchHalt 2018-05-06 16:38:00 +02:00
Dolu1990 294293cb70 Reintroduce debug plugin (instruction injector need optimisations) 2018-05-05 23:05:32 +02:00
Dolu1990 a50fbf0d7a Fix IBusCachedPlugin Pass all dhrystone tests 2018-04-30 13:35:17 +02:00
Dolu1990 4440047fb6 ICache compressed is working 2018-04-16 10:34:18 +02:00
Dolu1990 76352b44fa wip 2018-04-13 12:51:27 +02:00
Dolu1990 19d5d1ecf1 wip 2018-04-09 09:18:08 +02:00
Dolu1990 4dd2997ad5 wip 2018-04-09 09:12:30 +02:00
Dolu1990 e00c0750eb wip 2018-04-03 18:37:05 +02:00
Dolu1990 d9f2e03753 statuc prediction is fully funcitonnal 2018-04-02 17:43:58 +02:00
Dolu1990 76ca852478 Static prediction is fully functionnal 2018-04-02 17:43:06 +02:00
Dolu1990 0919308a8f IBusSimplePlugin add relaxedPcCalculation 2018-03-23 22:49:32 +01:00
Dolu1990 c48c7170e8 Added many pipelining option into IBusSimplePlugin 2018-03-23 19:07:03 +01:00
Dolu1990 351ad10925 RVC Add dhrystone regressions (PASS) 2018-03-21 23:36:57 +01:00
Dolu1990 0c7c2a1fba IBusPlugin add support of bus error when using compressed instruction 2018-03-21 22:34:54 +01:00
Dolu1990 31a464ffdc VexRiscv now pass Riscv-test compressed stuff 2018-03-21 20:50:07 +01:00
Dolu1990 af638e7bde RV32IC is passing some of the compressed Riscv-test tests 2018-03-21 20:30:09 +01:00
Dolu1990 f872d599e2 Add decodePcGen 2018-03-20 18:34:36 +01:00
Dolu1990 1fb138de1f IBusSimplePlugin fully functional Need to restore branch prediction 2018-03-20 00:01:28 +01:00
Dolu1990 ac74fb9ce8 iBusSimplePlugin done, DebugPlugin need minor rework 2018-03-18 13:21:21 +01:00
Dolu1990 64022557bf Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl 2018-03-15 18:56:25 +01:00
Dolu1990 63c1b738ff Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings 2018-03-14 00:56:23 +01:00
Dolu1990 d9b7426cde undo InOutWrapper from Murax 2018-03-14 00:47:23 +01:00
Dolu1990 2f8f4d5444 SpinalHDL 1.1.5 2018-03-13 15:45:56 +01:00
Dolu1990 7ea3e24183 update readme perf 2018-03-10 18:37:38 +01:00
Dolu1990 91031f8d75 DivPlugin is now based MulDivIterativePlugin (Smaller) 2018-03-10 13:31:35 +01:00
Dolu1990 f133e69fed fix readme toc 2018-03-10 13:04:48 +01:00
Dolu1990 578e54376a Add MulDivIterativePlugin in readme 2018-03-10 12:57:42 +01:00
Dolu1990 e437a1d44e Add division support in the MulDivInterativePlugin 2018-03-09 22:41:47 +01:00
Dolu1990 36438bd306 iterative mul improvments 2018-03-09 20:00:50 +01:00
Dolu1990 674ab2c594 experimental iterative mul/div combo 2018-03-09 19:07:26 +01:00
Dolu1990 5228a53293 MuraxSim improve simulation Speed 2018-03-06 12:20:39 +01:00
Dolu1990 9b2cd7b234 MuraxSim add switch 2018-03-06 12:17:15 +01:00
Dolu1990 53970dd284 SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
2018-03-05 14:34:59 +01:00
Dolu1990 b159ccf8ed
Update README.md 2018-02-27 22:43:53 +01:00
Dolu1990 ccad64def5 Pipeline CSR isWrite 2018-02-26 10:19:33 +01:00