Charles Papon
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3fc0a74102
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Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature
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2019-10-11 00:22:44 +02:00 |
|
Charles Papon
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51d22d4a8c
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Merge remote-tracking branch 'origin/cfu' into dev
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2019-10-10 15:00:43 +02:00 |
|
Charles Papon
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6ed41f7361
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Improve CSR FMax
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2019-09-16 13:53:55 +02:00 |
|
Charles Papon
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d94cee13f0
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Add dummy decoding, exception code/tval
Add Cpu generation code
Add support for always ready rsp
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2019-09-05 19:06:28 +02:00 |
|
Charles Papon
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5ac443b745
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Manage cases where a rsp buffer is required
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2019-09-05 10:41:45 +02:00 |
|
Dolu1990
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6951f5b8e6
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CfuPlugin addition
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2019-09-05 10:41:45 +02:00 |
|
Dolu1990
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84602f89b0
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Merge pull request #80 from antmicro/fix_litex_target
Fix handling LiteX uart and timer.
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2019-09-05 10:41:45 +02:00 |
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Dolu1990
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0efcaa505d
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Merge pull request #79 from antmicro/litex_target
Litex target
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2019-09-05 10:41:45 +02:00 |
Mateusz Holenko
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86f5af5ca9
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Fix handling LiteX uart and timer.
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2019-09-05 10:41:45 +02:00 |
|
Charles Papon
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94f1707d65
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Merge branch 'dev'
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2019-09-05 10:41:45 +02:00 |
|
Mateusz Holenko
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8813e071bc
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Add `litex` target
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
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2019-09-05 10:41:45 +02:00 |
|
Mateusz Holenko
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64a2815544
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Create makefile targets
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
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2019-09-05 10:41:45 +02:00 |
|
Mateusz Holenko
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e76435c6c6
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Allow to set custom DTB/OS_CALL addresses
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
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2019-09-05 10:41:45 +02:00 |
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Mateusz Holenko
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c8280a9a88
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Allow to set custom RAM base address for emulator
This is needed when loading the emulator to RAM
with an offset.
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2019-09-05 10:41:45 +02:00 |
|
Charles Papon
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b65ef189eb
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sync with SpinalHDL SDRAM changes
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2019-08-29 16:03:20 +02:00 |
|
Charles Papon
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a2569e76c0
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Update sdram ctrl package
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2019-07-08 11:23:48 +02:00 |
|
Charles Papon
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624c641af5
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xip refractoring
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2019-06-28 10:23:39 +02:00 |
|
Charles Papon
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b2e06ae198
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Back into unreleased SpinalHDL
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2019-06-17 17:19:11 +02:00 |
|
Charles Papon
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1257b056dc
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Revert "test only dynamic_target for intensive test"
This reverts commit 635ef51f82.
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2019-06-16 18:24:59 +02:00 |
|
Charles Papon
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12c3ab16ae
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Update readme perf
|
2019-06-16 18:07:04 +02:00 |
|
Charles Papon
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635ef51f82
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test only dynamic_target for intensive test
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2019-06-16 17:43:07 +02:00 |
|
Charles Papon
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9656604848
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rework dynamic_target failure correction
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2019-06-16 17:42:39 +02:00 |
|
Charles Papon
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4cf7e5b98f
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SpinalHDL 1.3.6
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2019-06-16 00:42:59 +02:00 |
|
Charles Papon
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60c9c094a7
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Merge remote-tracking branch 'origin/rework_jump_flush' into dev
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2019-06-15 18:09:38 +02:00 |
|
Charles Papon
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46e9d5566a
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Merge branch 'rework_jump_flush'
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2019-06-15 18:05:04 +02:00 |
|
Charles Papon
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7c3c4e8c81
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Update readme benches
|
2019-06-15 14:23:09 +02:00 |
|
Charles Papon
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a3a0c402bc
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Remove broken freertos test and add zephyr instead
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2019-06-15 10:46:10 +02:00 |
|
Charles Papon
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617f4742cd
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Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch
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2019-06-14 08:13:22 +02:00 |
|
Charles Papon
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d603de1bfe
|
Fix recent changes
|
2019-06-13 16:55:24 +02:00 |
|
Charles Papon
|
c8ab99cd0b
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Cleaning and remove BlockQ regression
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2019-06-12 00:00:38 +02:00 |
|
Charles Papon
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21ec368927
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Fix DYNAMIC_TARGET by fixing decode PC updates
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2019-06-11 19:56:33 +02:00 |
|
Charles Papon
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afbf0ea777
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Fix regression makefile
|
2019-06-11 01:05:49 +02:00 |
|
Charles Papon
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066ddc23e6
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Add regression concurrent os executions flag to avoid running debug plugin tests
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2019-06-11 00:22:38 +02:00 |
|
Charles Papon
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21c8933bbb
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Fix DYNAMIC_TARGET prediction correction in BranchPlugin
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2019-06-11 00:12:29 +02:00 |
|
Charles Papon
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5b53440d27
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DYNAMIC_TARGET prediction datapath/control path are now splited
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2019-06-10 22:20:32 +02:00 |
|
Charles Papon
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0e95154869
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individual regression : more env control
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2019-06-10 21:01:41 +02:00 |
|
Charles Papon
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bd46dd88aa
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Fix RVC fetcher pc branches
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2019-06-10 20:48:04 +02:00 |
|
Charles Papon
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24e1e3018c
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Fix exception handeling
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2019-06-09 23:40:37 +02:00 |
|
Charles Papon
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5243e46ffb
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Fix BranchPlugin when SRC can have hazard in execute stage
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2019-06-09 20:15:36 +02:00 |
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Charles Papon
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af0755d8cf
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rework flush with flushNext and flushIt
static branch prediction jump do not depend on stage fireing anymore
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2019-06-09 15:44:05 +02:00 |
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Charles Papon
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0e2d40c37f
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Merge remote-tracking branch 'origin/pipelinedInterrupt'
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2019-06-09 12:29:20 +02:00 |
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Charles Papon
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357681a5c6
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csrPlugin add pipelinedInterrupt, set by default
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2019-06-08 22:22:16 +02:00 |
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Charles Papon
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0df4ec45ad
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Merge remote-tracking branch 'origin/master' into dev
# Conflicts:
# build.sbt
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2019-06-05 00:35:41 +02:00 |
|
Charles Papon
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56f7c27d18
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Fix WFI. Not sensitive anymore to global interrupt enables, delegation and privilege
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2019-06-05 00:32:38 +02:00 |
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Dolu1990
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64e8919e89
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Update README.md
Add litex repo
|
2019-05-28 11:28:07 +02:00 |
|
Charles Papon
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38a464a829
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DataCache now allocate ways randomly
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2019-05-25 00:28:30 +02:00 |
|
Charles Papon
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4a40184b35
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Add cache Bandwidth counter, previous commit was about random instruction cache way allocation
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2019-05-25 00:22:27 +02:00 |
|
Charles Papon
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94606d38e2
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Add cache bandwidth counter
|
2019-05-25 00:21:48 +02:00 |
|
Charles Papon
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206c7ca638
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Fix Bmb datacache bridge
|
2019-05-24 00:22:58 +02:00 |
|
Charles Papon
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f6f94ad7c1
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Fix InstructionCache Bmb bridge
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2019-05-22 19:03:26 +02:00 |