Commit Graph

546 Commits

Author SHA1 Message Date
Dolu1990 7ed6835e97 Add C++ VexRiscv model to cross check the hardware simulation 2018-08-22 02:08:55 +02:00
Dolu1990 38af5dbdd5 riscv emulator WIP (RVC missing) 2018-08-21 01:03:51 +02:00
Dolu1990 dca1e5f438 revert RVC from murax 2018-08-17 23:12:45 +02:00
Dolu1990 f8c8643aa5 Merge remote-tracking branch 'origin/reworkFetcher' 2018-08-17 21:26:00 +02:00
Dolu1990 8ebb3af4fc Merge remote-tracking branch 'origin/master' into reworkFetcher
Conflicts:
	README.md
	src/main/scala/vexriscv/TestsWorkspace.scala
	src/test/scala/vexriscv/Play.scala
2018-08-17 20:56:51 +02:00
Dolu1990 9c7e089329 Fix ExternalInterruptArrayPlugin CSR ids 2018-08-17 20:38:33 +02:00
Dolu1990 819da2d0b4 remove freertos from travisautomated regressions tests 2018-08-17 20:07:09 +02:00
Dolu1990 1d3ac7830b restore tests without CSR catch all 2018-08-17 19:33:41 +02:00
Dolu1990 330ee14a23 final fetchRework commit ? 2018-08-17 19:13:23 +02:00
Dolu1990 91773ec7d5 Sync, Seem to pass all except dynamic_o0 which is probably a freertos test setup issue 2018-08-14 11:51:53 +02:00
Dolu1990 7ab04a128d
Merge pull request #34 from mithro/master
More README fixes
2018-07-21 18:38:57 +02:00
Dolu1990 50f6836100
Merge pull request #29 from mcmasterg/sudo_newline
README.md: add missing newline
2018-07-21 18:10:21 +02:00
Tim 'mithro' Ansell 373a3fcb90 README: Small improvement to text.
Fixes #31.
2018-07-21 09:08:29 -07:00
Tim 'mithro' Ansell ccde67bb67 README: Strip trailing white space. 2018-07-21 09:03:22 -07:00
Dolu1990 53cde3731b
Merge pull request #33 from mithro/master
Improve the Murax example for the iCE40-hx8k_breakout_board
2018-07-21 12:33:53 +02:00
Dolu1990 dbda31ad15
Merge pull request #30 from mithro/mithro-patch-1
Two minor fixes to README.md
2018-07-21 12:15:29 +02:00
Tim 'mithro' Ansell 1c5ee779ef Generate Murax with the flashy program. 2018-07-20 19:04:59 -07:00
Tim 'mithro' Ansell acbce9fb57 Adding a README file with images.
Should make it much easier to get started.
2018-07-20 19:04:41 -07:00
Tim 'mithro' Ansell 051d0c27d4 Rename example makefiles to more normal `Makefile`. 2018-07-20 18:31:13 -07:00
Tim 'mithro' Ansell 5465c0d4c0 Adding sudo-prog to hx8k_breakout_board example. 2018-07-20 18:30:26 -07:00
Tim Ansell 14e8254135
Add link to SBT source
In case you can't install via the apt source.
2018-07-20 17:16:47 -07:00
Tim Ansell 71950d72d1
Fix missing new line. 2018-07-20 17:14:46 -07:00
John McMaster 93d8a38664 README.md: add missing newline
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
2018-07-11 11:28:59 -07:00
Dolu1990 32fe1dcbd4 Add google cloud VM regressions scripts 2018-07-07 21:47:09 +02:00
Dolu1990 ce54fd78e4 wip 2018-07-07 11:40:02 +02:00
Dolu1990 3ea4f28354 wip 2018-07-07 11:39:42 +02:00
Dolu1990 9c1a8ea219 Fix EPC
Fix Freertos binaries
wip
2018-07-03 23:17:32 +02:00
Dolu1990 ffe5fa23f0 wip 2018-06-25 09:36:07 +02:00
Dolu1990 d73aa9ce00 rework csr exception/interrupt handeling wip 2018-06-24 00:14:55 +02:00
Dolu1990 dd47db9ad0 wip 2018-06-20 12:35:12 +02:00
Dolu1990 8886f7e6d4 test wip 2018-06-19 16:15:42 +02:00
Dolu1990 6c673b0749
Merge pull request #27 from tomverbeure/typos
README language
2018-06-19 11:18:28 +02:00
Tom Verbeure 43ab18fb83 Unrool -> Unroll 2018-06-19 02:02:43 -07:00
Tom Verbeure 68cc141401 Language 2018-06-19 01:53:31 -07:00
Tom Verbeure dda9fe76e2 an -> a 2018-06-19 01:41:24 -07:00
Tom Verbeure 8d22f74c83 Language 2018-06-19 01:39:37 -07:00
Tom Verbeure 4e9e8b3e55 Language 2018-06-18 17:19:37 -07:00
Tom Verbeure 5c9c43aa00 Language 2018-06-18 17:09:29 -07:00
Dolu1990 1090111a6f TestIndividual is now fully random 2018-06-15 13:00:59 +02:00
Dolu1990 b2cd8c5314 Fix exception pipelining 2018-06-15 13:00:26 +02:00
Dolu1990 83864710a3 Fix IBusCached single cycle interaction with mmu bus
Add random test configs
2018-06-09 08:40:19 +02:00
Dolu1990 d10bcbfbbb
Update README.md 2018-06-08 19:06:30 +02:00
Dolu1990 505a92916a
Update README.md 2018-06-08 18:00:22 +02:00
Dolu1990 4e73d4ff7d
Update README.md 2018-06-08 12:43:33 +02:00
Dolu1990 d9a049aa72
Update README.md 2018-06-08 12:31:55 +02:00
Dolu1990 08a1212fca Add DBus simple/cached regressions 2018-06-07 02:31:18 +02:00
Dolu1990 6bc5431fcd Add iBusCached regressions 2018-06-07 00:57:26 +02:00
Dolu1990 5e7dd02bf7 Fix relaxedPc/DYNAMIC_TARGET interaction 2018-06-06 18:30:30 +02:00
Dolu1990 dc968020c4 Fix relaxedBusCmdValid pendingCmd overflow 2018-06-06 15:20:37 +02:00
Dolu1990 7768f065e4 Add many cpu configs on regressions tests (some config are broken) 2018-06-06 02:23:07 +02:00