Hardware/VexRiscv
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Author SHA1 Message Date
Dolu1990
b0f7f37ac8 D$ now support memDataWidth > 32 2020-05-04 12:54:16 +02:00
Dolu1990
93b386e16e litex smp cluster now use OO decoder 2020-05-02 23:44:58 +02:00
Dolu1990
f0745eb0d9 update SMP line size to 64 bytes 2020-05-02 23:44:27 +02:00
Dolu1990
09ac23b78f Fix SMP fence lock when 4 stages CPU 2020-05-01 12:45:16 +02:00
Dolu1990
f5f30615ba Got litex SMP cluster to work on FPGA 2020-05-01 11:14:52 +02:00
Dolu1990
dc0da9662a Update SMP fence (final) 2020-05-01 11:14:11 +02:00
Dolu1990
7c50fa6d55 SmpCluster now use i$ line of 64 bytes 2020-04-29 14:03:00 +02:00
Dolu1990
9e9d28bfa6 d$ now implement consistancy hazard by using writeback redo 2020-04-29 14:02:41 +02:00
Dolu1990
86e0cbc1f3 I$ with memDataWidth > cpuDataWidth now mux memWords into cpuWords before the decode stage by default. Add twoCycleRamInnerMux option to move that to the decode stage 2020-04-29 13:59:43 +02:00
Dolu1990
7b80e1fc30 Set SMP workspace to use i$ memDataWidth of 128 bits 2020-04-28 22:11:41 +02:00
Dolu1990
eee9927baf IBusCachedPlugin now support memory data width multiple of 32 2020-04-28 22:10:56 +02:00
Dolu1990
23b8c40cab update travis verilator 2020-04-28 16:19:00 +02:00
Dolu1990
03a0445775 Fix SMP for configuration without writeback stage. 
Include SMP core into the single core tests regressions
 2020-04-28 15:50:20 +02:00
Dolu1990
4a49b23636 Fix regression 2020-04-28 14:38:27 +02:00
Dolu1990
3ba509931c Add VexRiscvSmpLitexCluster with the required pipelining to get proper FMax 2020-04-27 17:38:06 +02:00
Dolu1990
5fd0b220cd CsrPlugin add openSbi config 2020-04-27 17:37:30 +02:00
Dolu1990
0c59dd9ed3 SMP fence now ensure ordering for all kinds of memory transfers 2020-04-27 17:37:15 +02:00
Dolu1990
3fb123a64a fix withStall 2020-04-21 21:20:54 +02:00
Dolu1990
3885e52bb7 Merge remote-tracking branch 'origin/dev' into smp 2020-04-21 17:21:48 +02:00
Dolu1990
4016b1fc52 Add sbt assembly 2020-04-21 17:18:08 +02:00
Dolu1990
056bf63866 Add more consistancy tests 2020-04-21 16:03:03 +02:00
Dolu1990
b389878d23 Add smp consistency check, fix VexRiscv invalidation read during write hazard logic 2020-04-21 12:18:10 +02:00
Dolu1990
0e55caacab deduplicae VexRiscv wishbone 2020-04-21 10:33:51 +02:00
Dolu1990
b383b4b98b Add commented usage of fromXilinxBscane2 2020-04-20 12:13:12 +02:00
Dolu1990
8e8b64feaa Got full linux / buildroot to boot in 4 cpu config 2020-04-19 19:49:26 +02:00
Dolu1990
a1b6353d6b workaround AMO LR/SC consistancy issue, but that need a proper fix 2020-04-19 19:48:57 +02:00
Dolu1990
ad2d2e411a Add tap less debug plugin bridges 2020-04-19 17:56:33 +02:00
Dolu1990
af128ec9eb revert to 4 cpu 2020-04-18 01:27:35 +02:00
Dolu1990
4a49e6d91f initialize the clint in sim 2020-04-18 01:26:31 +02:00
Dolu1990
befecc7ed6 cleaning 2020-04-18 00:51:57 +02:00
Dolu1990
8c0e534c6b Add openSBI test, seem to work fine 2020-04-18 00:51:47 +02:00
Dolu1990
ebe070f9dd
Update README.md 2020-04-17 19:58:54 +02:00
Dolu1990
d5a52caab8 fix smp test barrier 2020-04-16 17:27:27 +02:00
Dolu1990
d88d04dbc4 More SMP tests (barrier via AMO and LRSC) 2020-04-16 15:23:25 +02:00
Dolu1990
fd52f9ba50 Add smp.bin 2020-04-16 02:22:18 +02:00
Dolu1990
73c21177e5 Add VexRiscvSmpCluster, seem to work on simple case 2020-04-16 01:30:03 +02:00
Dolu1990
b9ceabf128 few fixes 2020-04-16 01:29:13 +02:00
Dolu1990
46207abbc4 dataCache now implement invalidation sync 2020-04-16 01:28:38 +02:00
Dolu1990
a00605b10c fix Briey verilator 2020-04-13 13:01:12 +02:00
Dolu1990
467a2bc488 refactor DBus invalidation, and add invalidation enable 2020-04-11 19:06:22 +02:00
Dolu1990
abbfaf6bcf regression : restore normal invalidation setup 2020-04-10 18:58:03 +02:00
Dolu1990
4a9b8c1f72 improve invalidation read during write hazard logic 2020-04-10 14:44:28 +02:00
Dolu1990
0ad0f5ed3f Add d$ invalidation tests 
fix d$ invalidation, linux OK
 2020-04-10 14:28:16 +02:00
Dolu1990
f71f360e32 Add SMP synthesis 2020-04-10 14:27:39 +02:00
Dolu1990
296cb44bc4 Add hardware AMO support using LR/SC exclusive 2020-04-09 20:12:37 +02:00
Dolu1990
1d0e180e1d Add GenTwoStage config and UltraScale synthesis 2020-04-09 20:11:56 +02:00
Dolu1990
861df664cf clean some AMO stuff 2020-04-08 18:48:01 +02:00
Dolu1990
6922f80a87 DataCache now implement fence operations 2020-04-08 18:12:13 +02:00
Dolu1990
9e1817a280 fix DataCache for config without invalidation 2020-04-07 20:05:24 +02:00
Dolu1990
0c8ea4a368 DataCache add invalidation feature 2020-04-07 19:18:20 +02:00