Hardware/VexRiscv
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Author SHA1 Message Date
Dolu1990
6cde5f9315 Better doc about iorange 2021-06-02 10:27:46 +02:00
Dolu1990
0272d66971 Fix CsrPlugin.redoInterface priority 2021-05-28 16:20:43 +02:00
Dolu1990
4490254d3d Csr/Mmu ensure implement that SFENCE_VMA flush the next instructions 
SAT flush reworked a bit too
 2021-05-28 13:35:52 +02:00
Dolu1990
4b0763b43d CsrPlugin.csrMapping now give names to inner signals 2021-05-27 10:40:55 +02:00
Dolu1990
6066d8bc26 CsrPlugin add API to implement CSR in a decoupled way. (very low level api) #174 2021-05-26 11:44:46 +02:00
Dolu1990
72328e7bc4 Arty now has RVC enabled ! 2021-05-25 15:59:02 +02:00
Dolu1990
1c3b9e93a2
Merge pull request #182 from rdolbeau/extra_config 
Make the [ID]TLB size configurable from Litex
 2021-05-12 13:54:27 +02:00
Dolu1990
fe739b907a Bench DecoderPlugin 2021-05-10 10:47:15 +02:00
Romain Dolbeau
1bd33a369e Make the [ID]TLB size configurable from Litex 2021-05-08 07:59:34 -04:00
Dolu1990
e78c0546a0 fix #178 2021-05-04 21:09:42 +02:00
Dolu1990
fa2899a1a2 Merge branch 'debugPlugin' into dev 2021-04-26 11:11:38 +02:00
Dolu1990
45e67ccf56 sync 2021-04-26 11:10:55 +02:00
Dolu1990
0a0998fcea #176 fix typo 2021-04-22 14:02:46 +02:00
Dolu1990
32e4ea406f update #176 when DebugPlugin ebreak are enabled it disable CsrPlugin ebreak. Also, DebugPlugin ebreak can be disabled via the debug bus. 2021-04-22 13:59:33 +02:00
Dolu1990
bfe65da1eb implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used. 2021-04-20 23:23:18 +02:00
Dolu1990
4e41654a84 remove eclipse plugin 2021-04-12 18:28:41 +02:00
Dolu1990
73893ce5d9 CfuPlugin names fixes 2021-04-02 09:20:26 +02:00
Dolu1990
a42c089119 IBusSimplePlugin ensure AHB persistance 2021-03-31 19:03:38 +02:00
Dolu1990
9ac6625ef3 FpuCore improve FMA rounding 2021-03-29 16:31:18 +02:00
Dolu1990
a8721b02de Add AES/FPU doc 2021-03-29 14:55:41 +02:00
Dolu1990
9462496386 Add rvc support and fix rvc with FPU 2021-03-25 14:14:19 +01:00
Dolu1990
6f481f51ef Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage) 2021-03-25 14:13:12 +01:00
Dolu1990
21c91c6b70 fpu now lift wfi 2021-03-24 16:21:37 +01:00
Dolu1990
925edd160e RVC implement RVF RVD 
Rework RVC_GEN
 2021-03-24 12:04:27 +01:00
Dolu1990
704423f27f
Merge pull request #167 from rdolbeau/support_FDwC 
Attempt at supporting C (ompressed) and F/D (floating-point) together
 2021-03-24 11:59:05 +01:00
Romain Dolbeau
8495fe3dde Attempt at supporting C (ompressed) and F/D (floating-point) together 2021-03-24 11:07:09 +01:00
Dolu1990
da458dea7e litex cluster add cpuPerFpu option 2021-03-23 20:00:50 +01:00
Dolu1990
80f64f0f9f litex better pipelining for better fmax, create one FPU for each 4 cores 2021-03-18 11:10:22 +01:00
Dolu1990
6956db2b21 fpu add schedulerM2sPipe optino 2021-03-18 11:10:22 +01:00
Dolu1990
099dea743b fpu cleanup 2021-03-18 10:54:51 +01:00
Dolu1990
f6e620196d litex add fpu suport 2021-03-17 13:19:41 +01:00
Dolu1990
1a0aa37d6f Merge branch 'fiber' into dev 2021-03-17 10:02:09 +01:00
Dolu1990
530554d19c fix fpu diagram 2021-03-16 14:52:57 +01:00
Dolu1990
e23687c45d Handle ClockDomain improvements 2021-03-16 14:46:30 +01:00
Dolu1990
02c572b6f1 fpu improve FMax and add asyncronus regfile support 2021-03-16 14:45:59 +01:00
Dolu1990
0d628b4706 fpu add doc 2021-03-16 14:44:31 +01:00
Dolu1990
5aa1f2e996 fpu improve pipline cycles 2021-03-15 17:27:14 +01:00
Dolu1990
341c159d06 data cache relax assert into error 2021-03-15 14:43:22 +01:00
Dolu1990
3a34b8dae2 Merge branch 'dev' into fiber 
# Conflicts:
#	src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
#	src/main/scala/vexriscv/plugin/MulPlugin.scala
 2021-03-15 10:35:02 +01:00
Charles Papon
ff4e5e4666 wipe generator 2021-03-11 18:02:02 +01:00
Charles Papon
adc37b269c FpuPlugin.pending is now 6 bits 2021-03-11 13:06:50 +01:00
Charles Papon
845cfcb966 DebugPlugin.fromBscane2 added 2021-03-10 20:35:44 +01:00
Charles Papon
67d2f72a4b fiber sync 2021-03-07 20:43:02 +01:00
Dolu1990
e384bfe145 fiber update 2021-03-05 22:04:20 +01:00
Dolu1990
fd234bbf9e fix cfu gen error 2021-03-05 09:41:05 +01:00
Dolu1990
aee8841438 CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck 2021-03-05 09:41:05 +01:00
Dolu1990
0530d22a1d sync 2021-03-04 16:06:18 +01:00
Dolu1990
caf1bde49b Add MuraxAsicBlackBox example 2021-03-04 10:16:45 +01:00
Dolu1990
4bdab667cc fpu fix cmd / commit race condition 2021-03-02 19:39:55 +01:00
Dolu1990
636d53cf63 fpu now track commits using a counter per pipeline per port 2021-03-02 16:13:12 +01:00