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1172 Commits

Author SHA1 Message Date
Dolu1990 d4b877d415 fpu vex cmp/fle works 2021-01-18 15:09:30 +01:00
Dolu1990 6cb498cdb2 fpu merge load/commit 2021-01-18 13:09:08 +01:00
Dolu1990 a9d8c0a19f fpu wip 2021-01-18 11:38:26 +01:00
Dolu1990 3cda7c1f1b fpu wip 2021-01-15 14:03:37 +01:00
Dolu1990 04499c0b76 FPU sqrt functional 2021-01-14 18:33:24 +01:00
Dolu1990 85dd5dbf8e fpu div functional, sqrt wip 2021-01-14 15:56:56 +01:00
Samuel Lindemer 5e6c645461 Distinguish between page faults from MMU and access faults from PMP 2021-01-14 09:45:38 +01:00
Dolu1990 8761d0d9ee FpuCore can add/mul/fma/store/load 2021-01-13 18:28:26 +01:00
Dolu1990 6e0be6e18c Cfu add state index and cfu index 2021-01-11 13:44:04 +01:00
Dolu1990 930bdf9dda DataCache increase syncPendingMax to 32 and use a sync queue instead of async one 2021-01-04 10:59:21 +01:00
Dolu1990 780ad01ac0 Add AES-instruction support 2020-12-21 11:52:55 +01:00
Dolu1990 d2855fcfca
Merge pull request #147 from lindemer/pmp 
Physical Memory Protection (PMP) plugin
 2020-12-11 15:22:28 +01:00
Dolu1990 c59499ec03 typo 2020-12-11 14:13:33 +01:00
Dolu1990 eaff52b264 Add comments to the AesPlugin 2020-12-11 13:51:10 +01:00
Dolu1990 6da09967f8 Add comments to the AesPlugin 2020-12-11 13:46:55 +01:00
Samuel Lindemer 7d699dcc13 Remove PMP from MachineOs test defaults 2020-12-10 09:42:27 +01:00
Samuel Lindemer f2ce2eab00 PMP plugin passes regression tests 2020-12-07 12:04:45 +01:00
Samuel Lindemer 763eebeeba Add TOR support, tests pass on GenZephyr 2020-12-04 17:13:31 +01:00
Samuel Lindemer 5cb5061d9b PMP passes test with GenZephyr, but pipeline flushes have been disabled 2020-12-03 17:29:31 +01:00
Dolu1990 9a6931a54c CfuPlugin improve writeback buffering 2020-12-03 16:21:52 +01:00
Samuel Lindemer 987de8fb6a Lock PMP address registers in golden model 2020-12-02 14:18:17 +01:00
Samuel Lindemer 14c39a0070 Merge remote-tracking branch 'upstream/master' into pmp 2020-12-02 14:08:32 +01:00
Samuel Lindemer 872aa19d83 Add PMP to golden model 2020-12-02 12:27:26 +01:00
Samuel Lindemer d5b1a8f565 Add PMP test to regression suite 2020-12-01 18:38:06 +01:00
Dolu1990 45ff78d068 VexRiscvSmpClusterGen.dBusCmdMasterPipe option added 2020-12-01 13:51:10 +01:00
Samuel Lindemer c5023ad973 Add PMP regression test 2020-12-01 09:10:24 +01:00
Dolu1990 1b65a9e523
remove libts-dev from readme 2020-11-30 16:11:00 +01:00
Samuel Lindemer 2d0ebf1ef5 Flush pipeline after PMP CSR writes 2020-11-25 15:38:34 +01:00
Dolu1990 e0ae46e794 Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 
# Conflicts:
#	src/main/scala/vexriscv/plugin/CsrPlugin.scala
 2020-11-18 14:43:24 +01:00
Dolu1990 832218dbec DBusCachedPlugin increase pendingMax to 64 to hide memory latency when saving a full context 2020-11-16 12:38:29 +01:00
Dolu1990 ba523c627a Fix Csr ReadWrite interration with DBusCachedPlugin execute halt 2020-11-16 12:37:48 +01:00
Dolu1990 dae633aa7d
Merge pull request #150 from banahogg/patch-1 
Update GCC prebuild instructions for sifive.com reorg
 2020-11-15 11:25:50 +01:00
banahogg d1691e9478
Update GCC prebuild instructions for sifive.com reorg 2020-11-14 17:31:50 -08:00
Dolu1990 c1b0869c21 AesPlugin is now little endian 2020-11-12 15:07:27 +01:00
Dolu1990 1b2a2ebaca DBusCachedPlugin miss decoded aquire fix 2020-11-12 15:07:07 +01:00
Dolu1990 05e725174c AesPlugin added, work with dropbear encryption, seem ok for decryption (barmetal) 2020-11-02 17:14:52 +01:00
Dolu1990 9abe19317d RegFilePlugin.x0Init do less assumption on other plugin behaviour 2020-11-02 17:01:17 +01:00
Samuel Lindemer 97fe279f7b Enable PMP register lock 2020-10-29 13:37:21 +01:00
Dolu1990 dc9246715d Do not allow jtag ebreak outside machine mode 2020-10-28 13:00:16 +01:00
Dolu1990 4209dc2792 Fix CsrPlugin privilege crossing 2020-10-28 13:00:15 +01:00
Dolu1990 576e21d75d Do not allow jtag ebreak outside machine mode 2020-10-28 12:58:24 +01:00
Dolu1990 abebeaea1f Fix CsrPlugin privilege crossing 2020-10-28 12:57:20 +01:00
Samuel Lindemer fc2c8a7c37 Initial commit of PMP plugin 2020-10-27 09:38:58 +01:00
Dolu1990 fe342c347c CfuBusParameter has now a few default values 2020-10-23 11:06:24 +02:00
Dolu1990 d490f903ea
Merge pull request #145 from zeldin/bigendian2 
Update big endian instruction encoding
 2020-10-21 12:56:56 +02:00
Marcus Comstedt 6c8e97f825 Update big endian instruction encoding 
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the
RISC-V Instruction Set Manual, the wording was changed from requiring
"natural endianness" of instruction parcels to require them to be
little endian.

Update the big endian instruction pipe to reflect the newer requirement.
 2020-10-20 18:05:31 +02:00
Dolu1990 4ece59385d DataCache split redo / refilling execute stage halt 2020-10-19 18:12:20 +02:00
Dolu1990 e58daee088 SpinalHDL++ 2020-10-16 11:25:25 +02:00
Dolu1990 ec55187033 improve LightShifterPlugin arbitration halt timings 2020-10-09 11:37:48 +02:00
Dolu1990 bbaa0520c0
Fix UserInterruptPlugin interrupt enable 2020-10-09 10:45:23 +02:00