28 commits

Author	SHA1	Message	Date
Charles Papon	633e057d11	Split machine os regression in two smaller parts	2019-04-21 20:30:58 +02:00
Dolu1990	d18dcc0540	Update regression.mk ... reduce linux regression time a bit	2019-04-21 13:49:05 +02:00
Dolu1990	fc4c078f17	Update regression.mk ... Reduce machine os time	2019-04-21 13:36:25 +02:00
Charles Papon	7e91b5e446	Fix travis	2019-04-21 12:55:01 +02:00
Charles Papon	963805ad48	Bring freertos back in tests ... Better travis test range	2019-04-21 12:50:28 +02:00
Charles Papon	3b0f2e9551	better travis timings ... travis job naming reduce verilator cache size Fix dcache test timeout travis cleaning travis wip verilator wip fix java 10 compilation Travis wip travis rework	2019-04-20 14:56:56 +02:00
Tim Ansell	7594cbd902	Fixing images in README in iCE40-hx8k_breakout_board_xip directory too.	2019-02-22 14:57:07 -08:00
Tim Ansell	5c6cc29304	Fixing other image.	2019-02-22 14:55:18 -08:00
Tim Ansell	c9f4a09de0	Fix image in README.	2019-02-22 14:52:09 -08:00
Dolu1990	dcdfa79024	fix run-main into runMain	2019-01-03 20:07:38 +01:00
Dolu1990	a2d3cfbfc1	Remove unused file	2018-09-27 00:56:20 +02:00
Dolu1990	6dde73f97c	Murax demo with XIP is now fully defined in SpinalHDL	2018-09-27 00:55:30 +02:00
Dolu1990	1e3b75ef1d	xip typo	2018-09-23 22:06:21 +02:00
Dolu1990	ff1d1072a7	XIP is physicaly working on murax	2018-09-19 00:09:14 +02:00
Dolu1990	b51ac03a5e	murax xip flash integration wip	2018-09-18 16:53:26 +02:00
Tim 'mithro' Ansell	1c5ee779ef	Generate Murax with the flashy program.	2018-07-20 19:04:59 -07:00
Tim 'mithro' Ansell	acbce9fb57	Adding a README file with images. ... Should make it much easier to get started.	2018-07-20 19:04:41 -07:00
Tim 'mithro' Ansell	051d0c27d4	Rename example makefiles to more normal Makefile.	2018-07-20 18:31:13 -07:00
Tim 'mithro' Ansell	5465c0d4c0	Adding sudo-prog to hx8k_breakout_board example.	2018-07-20 18:30:26 -07:00
Dolu1990	b3564e1b7e	Fix Murax script flow (without rom file)	2018-01-21 15:39:10 +01:00
Dolu1990	3b3bbd48b9	SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files	2018-01-20 18:29:33 +01:00
Dolu1990	c3d950fb13	Clean script folder	2017-12-29 13:18:14 +01:00
Jakob Bornecrantz	617a2948d0	Port to iCE40HX8K-EVB	2017-12-27 21:21:55 +00:00
Charles Papon	c033b32fc9	scripts/murax remove jtag pullup which apparently break the functionality	2017-08-03 23:59:48 +02:00
Charles Papon	d962406b26	scripts/murax better makefile, add pullup on jtag interface	2017-08-03 23:22:57 +02:00
Charles Papon	568c7d1365	Update murax readme	2017-07-31 13:57:34 +02:00
Charles Papon	c16a53c388	Refractoring of some arbitration signals ... Add UART into Murax	2017-07-31 13:34:25 +02:00
Charles Papon	087e3dda89	Add Murax scripts	2017-07-29 22:43:43 +02:00