Charles Papon
|
ddf0f06834
|
Add more delegation tests
Reduce dcache test duration
|
2019-04-05 22:56:12 +02:00 |
|
Charles Papon
|
acaa931e11
|
Rework CsrPlugin interrupt delegation
|
2019-04-05 22:55:42 +02:00 |
|
Charles Papon
|
9e72971ff0
|
Move user mode page fault checkes from iBus/dBus plugin into the MmuPlugin
SUM was in fact already supported
|
2019-04-05 21:34:44 +02:00 |
|
Charles Papon
|
82c894932a
|
update todolist
|
2019-04-05 20:04:28 +02:00 |
|
Charles Papon
|
aeb418a99e
|
Add dcache tests
|
2019-04-05 20:03:22 +02:00 |
|
Charles Papon
|
5a6665e57f
|
Fix DataCache flush on the last line
|
2019-04-05 20:02:57 +02:00 |
|
Charles Papon
|
8459d423b8
|
add icache flush test
|
2019-04-05 18:11:33 +02:00 |
|
Charles Papon
|
60a41bfc75
|
rework i$ flush
|
2019-04-05 18:11:10 +02:00 |
|
Charles Papon
|
f5d4e745c7
|
Look like precise fence.i isn't required in practice
|
2019-04-05 18:08:25 +02:00 |
|
Charles Papon
|
446e9625af
|
Centralised all todo in linux.scala
Sorted out fence fence.i instruction in iBus/dBus plugins.
Fixed MMU permitions while in used mode and bypassing the MMU
|
2019-04-05 12:17:29 +02:00 |
|
Charles Papon
|
888e1c0b8a
|
Fix RVC instruction cache xtval allignement
|
2019-04-05 01:08:57 +02:00 |
|
Charles Papon
|
8e6010fd71
|
Got the debug plugin working with the linux config (had to disable CSR ebreak)
|
2019-04-05 00:25:27 +02:00 |
|
Charles Papon
|
4f0a02594c
|
Change LR/SC to reserve the whole memory
Fix MPP access from other plugins
Got all the common configuration to compile and pass regression excepted the debugger one
First synthesis results
|
2019-04-04 20:34:35 +02:00 |
|
Charles Papon
|
f8b438d9dc
|
cleaning
|
2019-04-04 12:59:08 +02:00 |
|
Charles Papon
|
de1c9c6fea
|
Removing D$ reports
|
2019-04-03 14:47:00 +02:00 |
|
Charles Papon
|
3f7a859e07
|
Got multiway I$ D$ running linux fine.
|
2019-04-03 14:33:35 +02:00 |
|
Charles Papon
|
922c18ee49
|
Add data cache flush feature
|
2019-04-03 15:56:58 +02:00 |
|
Charles Papon
|
066f562c5e
|
Got the MMU refilling itself with datacache cached memory access instead of io accesses
|
2019-04-03 14:32:21 +02:00 |
|
Charles Papon
|
8be40e637b
|
#60 Got the new data cache design passing all tests and running linux
|
2019-04-02 23:44:53 +02:00 |
|
Charles Papon
|
fd4da77084
|
#60 Got the new instruction cache design passing the standard regressions
|
2019-04-02 00:26:53 +02:00 |
|
Charles Papon
|
bc0af02c97
|
#60 Got instruction cache running linux :D
|
2019-04-01 11:59:04 +02:00 |
|
Charles Papon
|
1dff9aff8a
|
#60 Fix interrupt causing fetch privilege issues
|
2019-04-01 10:47:54 +02:00 |
|
Charles Papon
|
e74a5a71eb
|
Better simulation console integration
|
2019-04-01 10:31:55 +02:00 |
|
Charles Papon
|
369a3d0f5f
|
#60 Sync everything, added much comment on the top of Linux.scala to help reproduce
|
2019-03-31 23:43:56 +02:00 |
|
Charles Papon
|
c7314cc606
|
Got buildroot login, userspace, commands working
Moved location of DTB, initrd. Will move again
Added getChar SBI in emulator
Added an QEMU mode in the emulator config.h, work with qemu riscv32 virt
|
2019-03-31 15:17:45 +02:00 |
|
Dolu1990
|
de500ad8f9
|
Add qemu command
|
2019-03-30 18:29:17 +01:00 |
|
Dolu1990
|
9383445e0b
|
Add a qemu option (wip)
|
2019-03-30 18:26:44 +01:00 |
|
Charles Papon
|
1a36f2689d
|
#60 Fix software model. Forgot physical address for on RVC instruction
|
2019-03-30 11:24:29 +01:00 |
|
Charles Papon
|
29980016f3
|
#60 Fix instruction fetch exception PC by forcing LSB to be zero
|
2019-03-30 10:10:25 +01:00 |
|
Dolu1990
|
9fff419346
|
Better fix
|
2019-03-29 09:18:44 +01:00 |
|
Dolu1990
|
391cff69d3
|
#60 should fix the first instruction fetch privilege after interrupt
|
2019-03-29 09:02:44 +01:00 |
|
Dolu1990
|
0c48729611
|
Sync impact less changes (asfar i know)
|
2019-03-29 08:43:15 +01:00 |
|
Dolu1990
|
ad27007c3c
|
DBusSimplePlugin AHB bridge add hazard checking, pass tests
|
2019-03-28 11:41:49 +01:00 |
|
Dolu1990
|
53c05c31c7
|
IBusSimplePlugin AHB bridge fix, pass tests
|
2019-03-28 10:12:42 +01:00 |
|
Dolu1990
|
b0522cb491
|
Add AhbLite3 simulation config
|
2019-03-28 08:32:12 +01:00 |
Tom Verbeure
|
6038730e53
|
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv
|
2019-03-27 19:49:09 -07:00 |
|
Dolu1990
|
9ac4998478
|
Fix emulator nested exception redirection privilege
|
2019-03-28 00:38:38 +01:00 |
|
Dolu1990
|
ac06111163
|
Fix MMU MPRV, Fix emulator nested exception
|
2019-03-27 22:58:30 +01:00 |
|
Dolu1990
|
0bed511a6c
|
Fix cacheless LR/SC xtval, did some SRC/ADD_SUB/ALU redesign
|
2019-03-27 18:58:02 +01:00 |
|
Dolu1990
|
43c3922a3d
|
Add prerequired stuff
|
2019-03-27 10:55:20 +01:00 |
|
Dolu1990
|
f113946e66
|
Added a neutral LINUX_SOC for sim purposes
|
2019-03-27 10:53:41 +01:00 |
|
Dolu1990
|
b69c474fa2
|
#60 user space reached
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
|
2019-03-27 00:26:51 +01:00 |
|
Dolu1990
|
7a9f7c4fb9
|
Untested cacheless buses to AHB bridges
|
2019-03-26 16:30:53 +01:00 |
|
Dolu1990
|
94fc2c3ecf
|
Fix some models missmatch
Add more SBI
Add hardware LR/SC support in dbus cacheless
|
2019-03-26 01:25:18 +01:00 |
|
Dolu1990
|
1c3fd5c38b
|
Fix mprv and add it into the softare model
|
2019-03-25 12:03:32 +01:00 |
|
Dolu1990
|
1ec11dc03d
|
Fix mprv
|
2019-03-25 11:47:56 +01:00 |
|
Dolu1990
|
c34f5413a3
|
Add MMU MPRIV for easier machinemode emulation #60
|
2019-03-25 10:30:13 +01:00 |
|
Dolu1990
|
d63c6818df
|
Merge pull request #67 from tomverbeure/manual
Some minor updated to the manual
|
2019-03-25 02:07:42 +01:00 |
|
Dolu1990
|
9d55283b3b
|
Machine mode emulator
|
2019-03-25 02:00:19 +01:00 |
|
Tom Verbeure
|
3d5e941aef
|
Merge branch 'master' of https://github.com/SpinalHDL/VexRiscv
|
2019-03-24 23:56:23 +00:00 |