Hardware/VexRiscv
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Author SHA1 Message Date
Dolu1990
ff760a0bf0 DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS) 2018-05-21 13:45:08 +02:00
Dolu1990
6c47a3b2a3 update key 2018-05-17 19:07:58 +02:00
Dolu1990
e63e57981e travis test upload 2018-05-17 19:04:35 +02:00
Dolu1990
042962c1ae Fix travis 2018-05-17 18:56:31 +02:00
Dolu1990
938ed6abf6 Add bintraykey 2018-05-17 18:52:21 +02:00
Dolu1990
81790c32b8 Add travis 2018-05-17 18:43:52 +02:00
Dolu1990
7ffbfab312 Reintroduce MMU feature (pass tests) 2018-05-16 20:32:12 +02:00
Dolu1990
35fbf177e2 Update to SpinalHDL 1.1.6 2018-05-16 12:12:09 +02:00
Dolu1990
c8cec59f1d Update IBusCachedPlugin parameters 2018-05-16 12:11:53 +02:00
Dolu1990
3b54ecf303 Restore two cycle instruction cache features 2018-05-15 23:03:33 +02:00
Dolu1990
4e7152ae5a IcestormFlow add ultraplus support 2018-05-14 20:18:53 +02:00
Dolu1990
df3d9ccb13 rework IBusSimplePlugin parameters 2018-05-14 10:31:40 +02:00
Dolu1990
c0271d382f More assertion (csrPlugin) 2018-05-14 10:13:44 +02:00
Dolu1990
9caa7163ae IBusSimplePlugin add relaxedBusCmdValid feature 2018-05-14 10:04:19 +02:00
Dolu1990
610bd01f3b remove rspStageGen 2018-05-14 09:21:28 +02:00
Dolu1990
7b37669a0f Add exception catch to iBusSimplePLugin (pass) 2018-05-09 18:43:48 +02:00
Dolu1990
acccbf40e2 RVC debug pass tets 2018-05-09 00:28:14 +02:00
Dolu1990
0056da1342 DebugPlugin work 2018-05-08 02:01:34 +02:00
Dolu1990
e65757e34c wip before moving the fetchHalt 2018-05-06 16:38:00 +02:00
Dolu1990
294293cb70 Reintroduce debug plugin (instruction injector need optimisations) 2018-05-05 23:05:32 +02:00
Dolu1990
a50fbf0d7a Fix IBusCachedPlugin Pass all dhrystone tests 2018-04-30 13:35:17 +02:00
Dolu1990
558af595a1 Add ice40 synthesis results 2018-04-26 13:14:37 +02:00
Dolu1990
bdcf3f6234 Add HexTools and add a Briey main which load the ram 2018-04-26 10:27:39 +02:00
Dolu1990
cfc324aa0f Allow csr mtvec to not have reset values 2018-04-24 23:33:48 +02:00
Dolu1990
a9cbc48eb2 PcManagerPlugin is can now handle an external reset vector signal 2018-04-24 23:11:11 +02:00
Dolu1990
c7d852c497 Merge remote-tracking branch 'origin/Wishbone' 2018-04-22 12:15:25 +02:00
Dolu1990
978eb9b6b2 DBusCachedPlugin add CSR info 2018-04-22 11:46:01 +02:00
Dolu1990
74f2a4194a Add ExternalInterruptArrayPlugin 2018-04-20 17:56:21 +02:00
Dolu1990
6598e82920 wishbone => word address, not byte address 2018-04-19 11:22:06 +02:00
Dolu1990
455607b6b4 Fix dBus IO access 2018-04-18 14:11:59 +02:00
Dolu1990
6e59ddcc73 Cached wishbone demo is passing regression tests 2018-04-18 13:51:33 +02:00
Dolu1990
b37fc3fcc8 Add VexRiscv Wishbone demo for sim (generation ok) 2018-04-18 12:54:20 +02:00
Dolu1990
a66efcb35b Add wishbone support for i$ / d$ (not tested) 2018-04-17 23:56:44 +02:00
Dolu1990
4440047fb6 ICache compressed is working 2018-04-16 10:34:18 +02:00
Dolu1990
76352b44fa wip 2018-04-13 12:51:27 +02:00
Dolu1990
19d5d1ecf1 wip 2018-04-09 09:18:08 +02:00
Dolu1990
4dd2997ad5 wip 2018-04-09 09:12:30 +02:00
Dolu1990
e00c0750eb wip 2018-04-03 18:37:05 +02:00
Dolu1990
d9f2e03753 statuc prediction is fully funcitonnal 2018-04-02 17:43:58 +02:00
Dolu1990
76ca852478 Static prediction is fully functionnal 2018-04-02 17:43:06 +02:00
Dolu1990
bd4d1eeb01 Update briey soc diagram 2018-03-24 13:49:50 +01:00
Dolu1990
0919308a8f IBusSimplePlugin add relaxedPcCalculation 2018-03-23 22:49:32 +01:00
Dolu1990
c48c7170e8 Added many pipelining option into IBusSimplePlugin 2018-03-23 19:07:03 +01:00
Dolu1990
925f6ae811
Update README.md 2018-03-22 15:25:40 +01:00
Dolu1990
cd4ffc2f3f
Update README.md 2018-03-22 15:24:56 +01:00
Dolu1990
7da85303dd
Update README.md 2018-03-22 14:40:08 +01:00
Dolu1990
351ad10925 RVC Add dhrystone regressions (PASS) 2018-03-21 23:36:57 +01:00
Dolu1990
0c7c2a1fba IBusPlugin add support of bus error when using compressed instruction 2018-03-21 22:34:54 +01:00
Dolu1990
31a464ffdc VexRiscv now pass Riscv-test compressed stuff 2018-03-21 20:50:07 +01:00
Dolu1990
af638e7bde RV32IC is passing some of the compressed Riscv-test tests 2018-03-21 20:30:09 +01:00