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VexRiscv
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1341 Commits

Author SHA1 Message Date
Dolu1990 bfe65da1eb implement #176 DebugPlugin.allowEBreak is now disabled until the debug bus is used. 2021-04-20 23:23:18 +02:00
Samuel Lindemer 79bc09e69a Decouple PMP and CSR plugins 2021-04-13 08:35:07 +02:00
Dolu1990 4e41654a84 remove eclipse plugin 2021-04-12 18:28:41 +02:00
Samuel Lindemer 15137742fc
Merge branch 'dev' into new_pmp 2021-04-12 13:23:10 +02:00
Samuel Lindemer 9e65b769cf Update README.md 2021-04-12 13:20:15 +02:00
Samuel Lindemer b41db0af93 Prevent PMP access from U-mode, fix tests 2021-04-12 13:20:15 +02:00
Samuel Lindemer bf399cc927 Initial commit of optimized PMP plugin 2021-04-12 13:20:15 +02:00
Dolu1990 21d24eb07f
Merge pull request #171 from tcal-x/cfu-spec 
CFU spec -- update immed data sent in place of RS2.
 2021-04-03 10:32:55 +02:00
Tim Callahan 36c896f95b Update CFU immed field to use sext([31:24]) to match spec. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2021-04-02 13:16:53 -07:00
Dolu1990 66f5c3079b CfuPlugin names fixes 2021-04-02 12:50:21 -07:00
Dolu1990 73893ce5d9 CfuPlugin names fixes 2021-04-02 09:20:26 +02:00
Dolu1990 a42c089119 IBusSimplePlugin ensure AHB persistance 2021-03-31 19:03:38 +02:00
Dolu1990 9ac6625ef3 FpuCore improve FMA rounding 2021-03-29 16:31:18 +02:00
Dolu1990 a8721b02de Add AES/FPU doc 2021-03-29 14:55:41 +02:00
Dolu1990 9462496386 Add rvc support and fix rvc with FPU 2021-03-25 14:14:19 +01:00
Dolu1990 6f481f51ef Fetcher.decompressor ensure that the decoded instruction do not mutate when the pipeline is stalled (fix FPU cmd fork for rvc without injector stage) 2021-03-25 14:13:12 +01:00
Dolu1990 21c91c6b70 fpu now lift wfi 2021-03-24 16:21:37 +01:00
Dolu1990 925edd160e RVC implement RVF RVD 
Rework RVC_GEN
 2021-03-24 12:04:27 +01:00
Dolu1990 704423f27f
Merge pull request #167 from rdolbeau/support_FDwC 
Attempt at supporting C (ompressed) and F/D (floating-point) together
 2021-03-24 11:59:05 +01:00
Romain Dolbeau 8495fe3dde Attempt at supporting C (ompressed) and F/D (floating-point) together 2021-03-24 11:07:09 +01:00
Dolu1990 da458dea7e litex cluster add cpuPerFpu option 2021-03-23 20:00:50 +01:00
Dolu1990 80f64f0f9f litex better pipelining for better fmax, create one FPU for each 4 cores 2021-03-18 11:10:22 +01:00
Dolu1990 6956db2b21 fpu add schedulerM2sPipe optino 2021-03-18 11:10:22 +01:00
Dolu1990 099dea743b fpu cleanup 2021-03-18 10:54:51 +01:00
Dolu1990 f6e620196d litex add fpu suport 2021-03-17 13:19:41 +01:00
Dolu1990 1a0aa37d6f Merge branch 'fiber' into dev 2021-03-17 10:02:09 +01:00
Dolu1990 530554d19c fix fpu diagram 2021-03-16 14:52:57 +01:00
Dolu1990 e23687c45d Handle ClockDomain improvements 2021-03-16 14:46:30 +01:00
Dolu1990 02c572b6f1 fpu improve FMax and add asyncronus regfile support 2021-03-16 14:45:59 +01:00
Dolu1990 0d628b4706 fpu add doc 2021-03-16 14:44:31 +01:00
Dolu1990 5aa1f2e996 fpu improve pipline cycles 2021-03-15 17:27:14 +01:00
Dolu1990 341c159d06 data cache relax assert into error 2021-03-15 14:43:22 +01:00
Dolu1990 3a34b8dae2 Merge branch 'dev' into fiber 
# Conflicts:
#	src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
#	src/main/scala/vexriscv/plugin/MulPlugin.scala
 2021-03-15 10:35:02 +01:00
Charles Papon ff4e5e4666 wipe generator 2021-03-11 18:02:02 +01:00
Charles Papon adc37b269c FpuPlugin.pending is now 6 bits 2021-03-11 13:06:50 +01:00
Charles Papon 845cfcb966 DebugPlugin.fromBscane2 added 2021-03-10 20:35:44 +01:00
Charles Papon 67d2f72a4b fiber sync 2021-03-07 20:43:02 +01:00
Dolu1990 75bbb28ef6
readme update verlator version 2021-03-06 19:49:23 +01:00
Dolu1990 e384bfe145 fiber update 2021-03-05 22:04:20 +01:00
Dolu1990 fd234bbf9e fix cfu gen error 2021-03-05 09:41:05 +01:00
Dolu1990 aee8841438 CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck 2021-03-05 09:41:05 +01:00
Dolu1990 ec507308e7 fix cfu gen error 2021-03-04 20:29:33 +01:00
Dolu1990 bdc52097b6 CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck 2021-03-04 20:15:01 +01:00
Dolu1990 0530d22a1d sync 2021-03-04 16:06:18 +01:00
Dolu1990 caf1bde49b Add MuraxAsicBlackBox example 2021-03-04 10:16:45 +01:00
Dolu1990 4bdab667cc fpu fix cmd / commit race condition 2021-03-02 19:39:55 +01:00
Dolu1990 636d53cf63 fpu now track commits using a counter per pipeline per port 2021-03-02 16:13:12 +01:00
Dolu1990 81c193af1f Improve subnormal/normal rounding 2021-02-26 16:32:42 +01:00
Dolu1990 de81da36eb Fpu fix a few div special cases 2021-02-25 19:39:57 +01:00
Dolu1990 de09ed3fcb fpu added exact div/sqrt implementations using iterative approaches 2021-02-25 15:28:38 +01:00