Dolu1990
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dd12047aa7
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Merge branch dev (SpinalHDL 1.6.1)
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2021-12-15 09:22:46 +01:00 |
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Dolu1990
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0539dd7110
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SpinalHDL 1.6.2
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2021-12-08 23:45:05 +01:00 |
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Dolu1990
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6c5908f7a3
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Merge pull request #220 from BLangOS/patch-1
Update DebugPlugin.scala: Add optional readback of hardware breakpoint values
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2021-11-15 09:25:00 +01:00 |
B.Lang
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411d946a58
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Update DebugPlugin.scala
Add readback of the hardware breakpoint values.
A new parameter is added to the plugin to switch readback on and off.
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2021-11-11 12:12:23 +01:00 |
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Dolu1990
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acf14385d8
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#213 disable pmp test with region overlapping
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2021-10-22 17:24:51 +02:00 |
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Dolu1990
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9df704cad9
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Merge pull request #213 from occheung/pmp-fix
PMP Plugin: Fix PMP region size & priority
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2021-10-21 10:13:21 +02:00 |
occheung
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a3807660e3
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pmp perm: revert to mux for priority
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2021-10-19 11:40:39 +08:00 |
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occheung
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df03c99ab2
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pmp_setter: fix mask generation
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2021-10-19 11:39:25 +08:00 |
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Dolu1990
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c3c3a94c5d
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IBusSimplePlugin can now use a Vec based buffer
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2021-10-13 16:26:16 +02:00 |
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Dolu1990
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97a3c1955b
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VexRiscvSmpCluster add d$ i$ less arg
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2021-10-11 11:57:39 +02:00 |
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Dolu1990
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35754a0709
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Fix BrieySim (SpinalSim)
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2021-09-25 13:28:37 +02:00 |
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Dolu1990
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8c0fbcadac
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Add BrieySim (SpinalSim)
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2021-09-25 13:18:55 +02:00 |
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Dolu1990
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5f5f4afbf2
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Briey revert RVC unwanted addition
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2021-09-22 15:01:08 +02:00 |
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Dolu1990
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b807254759
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Briey and Murax verilators now use FST instead of VCD
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2021-09-22 12:57:27 +02:00 |
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Dolu1990
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65cda95176
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Fix wishbone bridges with datawidth > 32
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2021-09-17 09:43:30 +02:00 |
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Dolu1990
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c1481ae244
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update ScopeProperty usages
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2021-09-16 19:08:41 +02:00 |
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Dolu1990
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42bb1ab591
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d$ / i$ toWishbone bridges can now be bigger than 32 bits
https://github.com/m-labs/VexRiscv-verilog/pull/12
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2021-09-15 11:36:51 +02:00 |
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Dolu1990
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68e704f309
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restore avalon d$ tests
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2021-09-02 15:42:33 +02:00 |
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Dolu1990
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efd3cd4737
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Merge branch 'master' into dev
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2021-09-02 14:16:07 +02:00 |
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Dolu1990
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cc9f3e753a
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Fix d$ toAxi bridge
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2021-09-02 14:14:42 +02:00 |
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Dolu1990
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bc561c30eb
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Add PmpPluginOld (support TOR)
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2021-09-01 11:27:12 +02:00 |
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Dolu1990
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5c7e4a0294
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#170 wishbone example now set dBusCmdMasterPipe
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2021-08-24 23:24:29 +02:00 |
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Dolu1990
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3deeab42fd
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VexRiscvSmpCluster config fix
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2021-08-10 12:14:42 +02:00 |
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Dolu1990
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805bd56077
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Fix VexRiscvBmbGenerator.hardwareBreakpointCount default value
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2021-07-30 16:51:07 +02:00 |
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Dolu1990
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671bd30953
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Update Bmb invalidate/sync parameters
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2021-07-28 13:44:04 +02:00 |
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Dolu1990
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ba8f5f966a
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Vfu typo
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2021-07-26 15:27:20 +02:00 |
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Dolu1990
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b717f228d6
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VfuPlugin wip
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2021-07-26 15:17:06 +02:00 |
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Dolu1990
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c242744d02
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CfuPlugin now only fork when the rest of the pipeline is hazard free
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2021-07-26 14:45:54 +02:00 |
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Dolu1990
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f3f9b79f9a
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VexRiscvSmpCluster earlyShifterInjection added
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2021-07-21 18:34:57 +02:00 |
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Dolu1990
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5fc4125763
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Merge branch 'dev'
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2021-07-20 11:21:11 +02:00 |
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Dolu1990
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3028c19389
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Fix #191 (data cache toAxi bridge)
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2021-07-20 11:20:53 +02:00 |
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Dolu1990
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5f2fcc7d0f
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Merge branch 'dev'
(SpinalHDL 1.6.0)
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2021-07-20 10:39:09 +02:00 |
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Dolu1990
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66bcd7fca7
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readme: add the tom link about JTAG and GDB
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2021-07-20 10:14:54 +02:00 |
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Dolu1990
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0cdad37fff
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VexRiscvSmpClusterGen now implement ebreak
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2021-07-11 21:55:33 +02:00 |
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Dolu1990
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91b3e79485
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SpinalHDL version++
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2021-07-11 21:55:13 +02:00 |
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Dolu1990
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a4c86130cc
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Update README.md
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2021-07-09 09:35:49 +02:00 |
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Dolu1990
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9bc7dce857
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Update README.md
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2021-07-08 09:47:54 +02:00 |
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Dolu1990
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28a75afe7a
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reduce regression time
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2021-07-05 14:17:59 +02:00 |
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Dolu1990
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c79357d1b2
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VexRiscvSmpClusterGen no support atomic less configs
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2021-07-05 12:38:54 +02:00 |
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Dolu1990
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a380c3a36c
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Merge branch 'spinal_1.4.4' into dev
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2021-07-05 11:37:53 +02:00 |
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Dolu1990
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551e76d244
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VexRiscvSmpCluster add a few options
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2021-07-02 19:04:30 +02:00 |
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Dolu1990
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3702ea03c0
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Fix github actions
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2021-06-23 11:48:53 +02:00 |
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Dolu1990
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df7ac05db9
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Update 2.13 compatibility
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2021-06-23 11:48:38 +02:00 |
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Dolu1990
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cdd8a7e94a
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add github action
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2021-06-23 09:04:35 +02:00 |
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Dolu1990
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1017b316b8
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version++
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2021-06-15 15:59:09 +02:00 |
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Dolu1990
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d67fe72de9
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Merge branch 'dev'
# Conflicts:
# build.sbt
# src/test/cpp/regression/main.cpp
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2021-06-15 15:54:13 +02:00 |
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Dolu1990
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1497001ebd
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Update FpuTest with the new rs1/rs2 store mapping
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2021-06-09 13:37:31 +02:00 |
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Dolu1990
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1ee45eeb0a
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More named signals
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2021-06-09 11:27:18 +02:00 |
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Dolu1990
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0e89ebeced
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Improve FPU rs1 timings
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2021-06-09 11:26:58 +02:00 |
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Dolu1990
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e1e1be5797
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exception code can now be bigger than 4 bits
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2021-06-08 12:19:08 +02:00 |