Dolu1990
dd42e30c61
Merge remote-tracking branch 'origin/master' into dev
2018-12-29 14:04:07 +01:00
Dolu1990
1da055dc34
Merge pull request #49 from cutephoton/avalon
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Avalon: Debug Clock Domain for JTAG
2018-12-23 16:27:50 +01:00
Brett Foster
961abb3cf1
Avalon: Debug Clock Domain for JTAG
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This change ensures that the clock domain for the JTAG interface
uses the debug plugin's domain. Otherwise, resetting the processor
will put the jtag debugger in to reset as well.
See SpinalHDL/VexRiscv#48
2018-12-22 07:58:59 -08:00
Dolu1990
76ebfb2243
Fix machine mode to supervisor delegation
2018-12-10 13:15:03 +01:00
Dolu1990
d9029c2efc
Fix #46 by filling missing return statements
2018-12-10 01:44:47 +01:00
Dolu1990
281d61bbe1
regression fix hex << dec #46
2018-12-09 16:37:16 +01:00
Dolu1990
1fbb81a4d9
regression fix delete [] #46
2018-12-09 15:40:02 +01:00
Dolu1990
cf80c63c22
fix travis
2018-12-08 15:16:17 +01:00
Dolu1990
f121ce1ed5
add sanity asserts in regression #46
2018-12-08 14:10:18 +01:00
Dolu1990
9330945623
fix regression makefile
2018-12-07 23:50:13 +01:00
Dolu1990
52419fd7ad
Regression remove dplus stuff #46
2018-12-07 23:47:49 +01:00
Dolu1990
68fdbe60cc
verilator regression fix missing fclose #46
2018-12-07 23:43:19 +01:00
Dolu1990
6334f430fe
Update README.md
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Fix #44
2018-12-04 19:07:51 +01:00
Dolu1990
eca54585b0
Fix hardware breakpoint
2018-12-04 16:57:24 +01:00
Dolu1990
ac1ed40b80
Move things into SpinalHDL lib
2018-12-01 18:25:18 +01:00
Dolu1990
3d71045159
DebugPlugin doesn't require memory/writeback stage anymore
2018-12-01 18:24:33 +01:00
Dolu1990
58d7a4784d
move HexTools into SpinalHDL lib
2018-11-30 17:39:33 +01:00
Dolu1990
b1b7da4f10
Rename SimpleBus into PipelinedMemoryBus
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Move PipelinedMemoryBus into SpinalHDL lib
2018-11-30 17:37:17 +01:00
Dolu1990
f54865bcb8
Merge remote-tracking branch 'origin/dev'
2018-11-29 22:43:26 +01:00
Dolu1990
2f6a2dfccc
Add configs setup in SimpleBusInterconnect
2018-11-29 16:14:45 +01:00
Dolu1990
7075e08d9f
Hazarplugin tell to branch plugin if the RS are hazardous in the execute stage
2018-11-24 13:38:54 +01:00
Dolu1990
c2b9544794
Allow iBusCached plugin to be used when no memory stage is present
2018-11-24 13:37:53 +01:00
Dolu1990
2d8d3d0566
Update readme
2018-11-22 22:49:16 +01:00
Dolu1990
f18696357f
SpinalHDL 1.2.2
2018-11-22 22:45:07 +01:00
Dolu1990
0086de9e36
Fix CsrPlugin catch illegalAccess
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Add dhrystone optimized divider
cleaning
2018-11-20 19:39:17 +01:00
Dolu1990
75d4d049d7
Add shadow regfile
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various cleaning
2018-11-16 17:06:11 +01:00
Dolu1990
cc48fc7403
add fenceiGenAsANop
2018-11-13 15:17:35 +01:00
Dolu1990
0d92a5e5cd
Add many little options to reduce area
2018-11-12 14:14:34 +01:00
Dolu1990
fb9ea11a5e
Allow VexRiscv to suppress the memory and the writeback stage, allowing to go downto a 2 stage CPU (FETCH_DECODE, EXECUTE)
2018-11-09 05:41:43 +01:00
Dolu1990
b12e15b112
branch/csr/muldiv minor improvments
2018-11-07 19:27:49 +01:00
Dolu1990
b7f3ee5e06
Fix CsrPlugin pipelined option
2018-11-05 16:22:41 +01:00
Dolu1990
662d76e3aa
csrPlugin : avoid using ALU to get SRC1 (which was useless)
2018-11-03 11:29:30 +01:00
Dolu1990
978232fd63
Optimise div iterative plugin done signal
2018-11-03 11:12:37 +01:00
Dolu1990
c8ac214097
Optimize CSR
2018-10-28 02:18:27 +02:00
Dolu1990
51de2b5820
SimpleBusInterconnect now adapte address width
2018-10-28 02:18:08 +02:00
Dolu1990
00bf84b7f8
Add SimpleBusInterconnect
2018-10-25 23:47:05 +02:00
Dolu1990
4ed4af6a3e
SrcPlugin add decodeAddSub option
2018-10-24 01:28:37 +02:00
Dolu1990
372063582c
Improve CsrPlugin CombinatorialPaths
2018-10-23 19:07:08 +02:00
Dolu1990
7096c63d50
Add more SimpleBus utilies
2018-10-23 17:46:31 +02:00
Dolu1990
7c0f2dc713
Add SimpleBus object
2018-10-20 12:39:30 +02:00
Morard Dany
85e696b286
CsrPlugin : Add mtvecModeGen
2018-10-16 14:53:41 +02:00
Dolu1990
1e64d71609
Merge remote-tracking branch 'origin/Supervisor' into dev
2018-10-16 13:09:17 +02:00
Dolu1990
905abd5aaa
Add wfiGenAsWait and wfiGenAsNop
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CsrPlugin cleaning
Much cleaning in general
Zephyr is running
2018-10-16 13:07:30 +02:00
Dolu1990
25c0a0ff6f
Add RVC into the readme
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Forgot to add RVC (compressed) support information into the readme
2018-10-13 09:57:13 +02:00
Dolu1990
f903df4b66
sync
2018-10-12 17:13:54 +02:00
Dolu1990
2b29690010
Clean branch plugin lsb bit calculation
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BranchPlugin doesn't try anymore to catch exception when RVC is on
2018-10-12 12:24:52 +02:00
Dolu1990
eea92154ae
fetcher force PC LSB to be zero
2018-10-12 12:02:52 +02:00
Dolu1990
0b8f6f6ed4
Fix broken C.LWSP reference_output
2018-10-12 12:02:02 +02:00
Dolu1990
594f7a8bf2
Seem to pass all risc-v compliance tests, excepted the C.LWSP which is a broken test
2018-10-11 22:19:17 +02:00
Dolu1990
8c25e73b9d
Fix DIV negative values divided by zero
2018-10-11 22:18:21 +02:00