Dolu1990
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b37fc3fcc8
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Add VexRiscv Wishbone demo for sim (generation ok)
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2018-04-18 12:54:20 +02:00 |
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Dolu1990
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a66efcb35b
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Add wishbone support for i$ / d$ (not tested)
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2018-04-17 23:56:44 +02:00 |
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Dolu1990
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4440047fb6
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ICache compressed is working
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2018-04-16 10:34:18 +02:00 |
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Dolu1990
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76352b44fa
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wip
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2018-04-13 12:51:27 +02:00 |
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Dolu1990
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19d5d1ecf1
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wip
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2018-04-09 09:18:08 +02:00 |
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Dolu1990
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4dd2997ad5
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wip
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2018-04-09 09:12:30 +02:00 |
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Dolu1990
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e00c0750eb
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wip
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2018-04-03 18:37:05 +02:00 |
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Dolu1990
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d9f2e03753
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statuc prediction is fully funcitonnal
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2018-04-02 17:43:58 +02:00 |
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Dolu1990
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76ca852478
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Static prediction is fully functionnal
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2018-04-02 17:43:06 +02:00 |
Dolu1990
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bd4d1eeb01
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Update briey soc diagram
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2018-03-24 13:49:50 +01:00 |
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Dolu1990
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0919308a8f
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IBusSimplePlugin add relaxedPcCalculation
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2018-03-23 22:49:32 +01:00 |
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Dolu1990
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c48c7170e8
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Added many pipelining option into IBusSimplePlugin
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2018-03-23 19:07:03 +01:00 |
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Dolu1990
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925f6ae811
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Update README.md
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2018-03-22 15:25:40 +01:00 |
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Dolu1990
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cd4ffc2f3f
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Update README.md
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2018-03-22 15:24:56 +01:00 |
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Dolu1990
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7da85303dd
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Update README.md
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2018-03-22 14:40:08 +01:00 |
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Dolu1990
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351ad10925
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RVC Add dhrystone regressions (PASS)
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2018-03-21 23:36:57 +01:00 |
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Dolu1990
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0c7c2a1fba
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IBusPlugin add support of bus error when using compressed instruction
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2018-03-21 22:34:54 +01:00 |
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Dolu1990
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31a464ffdc
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VexRiscv now pass Riscv-test compressed stuff
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2018-03-21 20:50:07 +01:00 |
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Dolu1990
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af638e7bde
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RV32IC is passing some of the compressed Riscv-test tests
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2018-03-21 20:30:09 +01:00 |
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Dolu1990
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f872d599e2
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Add decodePcGen
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2018-03-20 18:34:36 +01:00 |
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Dolu1990
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1fb138de1f
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IBusSimplePlugin fully functional Need to restore branch prediction
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2018-03-20 00:01:28 +01:00 |
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Dolu1990
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ac74fb9ce8
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iBusSimplePlugin done, DebugPlugin need minor rework
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2018-03-18 13:21:21 +01:00 |
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Dolu1990
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64022557bf
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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation for vhdl
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2018-03-15 18:56:25 +01:00 |
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Dolu1990
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63c1b738ff
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Add synthesis attribut to the PcManagerSimplePlugin to optimize the pc calculation inferation timings
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2018-03-14 00:56:23 +01:00 |
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Dolu1990
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d9b7426cde
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undo InOutWrapper from Murax
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2018-03-14 00:47:23 +01:00 |
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Dolu1990
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2f8f4d5444
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SpinalHDL 1.1.5
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2018-03-13 15:45:56 +01:00 |
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Dolu1990
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7ea3e24183
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update readme perf
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2018-03-10 18:37:38 +01:00 |
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Dolu1990
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91031f8d75
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DivPlugin is now based MulDivIterativePlugin (Smaller)
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2018-03-10 13:31:35 +01:00 |
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Dolu1990
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f133e69fed
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fix readme toc
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2018-03-10 13:04:48 +01:00 |
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Dolu1990
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578e54376a
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Add MulDivIterativePlugin in readme
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2018-03-10 12:57:42 +01:00 |
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Dolu1990
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e437a1d44e
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Add division support in the MulDivInterativePlugin
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2018-03-09 22:41:47 +01:00 |
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Dolu1990
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36438bd306
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iterative mul improvments
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2018-03-09 20:00:50 +01:00 |
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Dolu1990
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674ab2c594
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experimental iterative mul/div combo
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2018-03-09 19:07:26 +01:00 |
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Dolu1990
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5228a53293
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MuraxSim improve simulation Speed
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2018-03-06 12:20:39 +01:00 |
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Dolu1990
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9b2cd7b234
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MuraxSim add switch
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2018-03-06 12:17:15 +01:00 |
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Dolu1990
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53970dd284
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SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
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2018-03-05 14:34:59 +01:00 |
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Dolu1990
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b159ccf8ed
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Update README.md
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2018-02-27 22:43:53 +01:00 |
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Dolu1990
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ccad64def5
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Pipeline CSR isWrite
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2018-02-26 10:19:33 +01:00 |
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Dolu1990
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2b6185b063
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Decoding logic : Add primes duplication removal
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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2b6f43cef8
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Fix Murax memory mapping range
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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5260ad5c35
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Decoding lib cleaning
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2018-02-25 08:57:31 +01:00 |
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Dolu1990
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137b1ee32c
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Briey testbench, fix io_coreInterrupt to zero to avoid external interrupt set by random boots values
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2018-02-22 22:36:13 +01:00 |
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Dolu1990
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d957934949
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Fix ICache exception priority over miss reload
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2018-02-19 22:44:46 +01:00 |
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Dolu1990
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0270ee26fa
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Merge remote-tracking branch 'origin/reworkInstructionCache'
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2018-02-18 23:52:02 +01:00 |
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Dolu1990
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8ac4d72623
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Update readme
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2018-02-18 23:48:20 +01:00 |
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Dolu1990
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d0e963559a
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Update readme with the new ICache implementation
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2018-02-18 23:48:11 +01:00 |
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Dolu1990
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93110d3b95
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Add jump priority managment in PcPlugins
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2018-02-16 14:27:20 +01:00 |
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Dolu1990
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506e0e3f60
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New faster/smaller/multi way instruction cache design.
Single or dual stage
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2018-02-16 02:21:08 +01:00 |
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Dolu1990
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3853e0313b
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SynthesisBench cleaning/experiments
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2018-02-11 14:53:42 +01:00 |
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Dolu1990
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2a336c2812
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update readme
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2018-02-09 00:56:14 +01:00 |