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  • a6e89fe05c fpu vex regression goldenModel can now assert FPU interface Dolu1990 2021-02-19 17:55:56 +0100
  • 3f226b758c fpu fix exception flag handeling Dolu1990 2021-02-19 13:03:48 +0100
  • e504afbf18 fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined) Dolu1990 2021-02-19 11:26:28 +0100
  • 8537d18b16 fpu improve fmax Dolu1990 2021-02-17 16:35:52 +0100
  • 1e647f799c fpu Fix VexRiscv integration and add software f64 tests (pass) Dolu1990 2021-02-17 12:33:27 +0100
  • 06b7a91de4 MulPlugin fix buffer interraction with partial regfile bypass Dolu1990 2021-02-17 11:35:17 +0100
  • f180ba2fc9 fpu double fixes DataCache now support wide load/store Dolu1990 2021-02-16 15:38:51 +0100
  • 8b2a2afb6f VexRIscvSmpCluster add options Dolu1990 2021-02-16 14:42:31 +0100
  • 1752b9e6d6 DataCache.toBmb with aggregation sync path pipelined Dolu1990 2021-02-16 14:17:21 +0100
  • fe690528f7 MulPlugin.outputBuffer feature added Dolu1990 2021-02-16 14:16:57 +0100
  • 3b99090879 VexRiscvConfig.get added Dolu1990 2021-02-16 14:15:20 +0100
  • 7d3b35c32c fpu f64/f32 pass all tests Dolu1990 2021-02-12 14:48:44 +0100
  • 9a25a12879 fpu add FCVT_X_X Dolu1990 2021-02-11 17:40:35 +0100
  • 82dfd10dba fpu fix f32 tests for f64 fpu Dolu1990 2021-02-11 16:42:17 +0100
  • b6eda1ad7a fpu f64 load/store/mv/mul seems ok Dolu1990 2021-02-11 16:07:47 +0100
  • e97c2de837 fpu f64 wip Dolu1990 2021-02-10 19:27:26 +0100
  • 88dffc21f7 fpu f64 wip Dolu1990 2021-02-10 13:20:17 +0100
  • 889cc5fde2 fpu refractoring Dolu1990 2021-02-10 12:16:44 +0100
  • 1fe993ad10 fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully Dolu1990 2021-02-09 18:35:47 +0100
  • bf6a64b6b5 fpu sgnj / fclass / fmv pass Dolu1990 2021-02-08 15:29:50 +0100
  • bf0829231d fpu min max pass Dolu1990 2021-02-06 14:08:21 +0100
  • 008fadeaa9 fpu eq lt le pass testfloat Dolu1990 2021-02-06 13:20:27 +0100
  • 6170243283 fpu got exception flag right for add/sub/mul/i2f/f2i Dolu1990 2021-02-05 16:24:14 +0100
  • 7afe6cbef8
         Update .travis.yml travis_debug Dolu1990 2021-02-05 14:51:55 +0100
  • 130733ab08
         Update .travis.yml Dolu1990 2021-02-05 13:56:44 +0100
  • 3dfbe0057e
         Update .travis.yml Dolu1990 2021-02-05 11:54:14 +0100
  • f278900cbe VexRiscvSmpCluster can now set regfile read kind Dolu1990 2021-02-05 11:09:04 +0100
  • 0f1ca72171 fix synthesis bench Dolu1990 2021-02-04 12:41:31 +0100
  • 936e5823dc fpu test wip Dolu1990 2021-02-04 12:41:49 +0100
  • 3710fd3492 fix synthesis bench Dolu1990 2021-02-04 12:41:31 +0100
  • 200faed1ae travis debug Dolu1990 2021-02-03 21:41:23 +0100
  • 02b5b9b05c fpu load subnormal and i2f now use single cycle shifter Dolu1990 2021-02-03 16:48:09 +0100
  • 8e7e736e3e Merge branch 'dev' into fpu Dolu1990 2021-02-03 16:06:17 +0100
  • 8eb8356dea fpu wip Dolu1990 2021-01-15 14:03:37 +0100
  • 1d0eecdcb0 fpu f2i rounding ok and full shifter Dolu1990 2021-02-03 14:27:52 +0100
  • ef011fa0d4 fpu moved 1 bit from round to mantissa Dolu1990 2021-02-02 11:29:35 +0100
  • a87cb202b1 fpu i2f rounding ok Dolu1990 2021-02-01 16:12:38 +0100
  • d92adfbad0 SpinalHDL version++ Dolu1990 2021-02-01 15:20:57 +0100
  • 6ee45a1014 SpinalHDL version++ Dolu1990 2021-02-01 12:28:07 +0100
  • 36b3cd9188 Merge branch 'dev' Dolu1990 2021-02-01 12:19:21 +0100
  • 98eaeaabc8
         fix regression.mk typo Dolu1990 2021-01-30 22:34:54 -0100
  • 6aa6191240 Merge branch 'master' into dev Dolu1990 2021-01-30 20:30:21 +0100
  • c51b0fcafe fpu mul now pass all roundings Dolu1990 2021-01-29 22:30:19 +0100
  • 0997592768 fpu mul sems all good excepted subnormal rounding Dolu1990 2021-01-29 16:13:49 +0100
  • 3c4df1e963 fpu moved overflow rounding to writeback Dolu1990 2021-01-29 14:37:52 +0100
  • fc3e6a6d0a fpu add rounding is ok excepted infinity result Dolu1990 2021-01-28 20:26:43 +0100
  • 1ae84ea83b fpu added proper rounding for add (need to manage substraction) Dolu1990 2021-01-28 00:25:16 +0100
  • 195e4c422d fpu now integrate f2i shifter withing the subnormal shifter Dolu1990 2021-01-27 12:11:30 +0100
  • 444bcdba0a fpu merged i2f with load pipeline Dolu1990 2021-01-26 15:28:09 +0100
  • 3334364f5f fpu added more tests for min max sqrt div Dolu1990 2021-01-26 12:50:23 +0100
  • f818fb3ba4 fpu got proper subnormal support, pass add/mul Dolu1990 2021-01-26 10:49:53 +0100
  • d6e8a5ef22 VexRiscvSmpLitex options refractoring Dolu1990 2021-01-23 20:16:58 +0100
  • ce143e06f2 VexRiscvSmpLitex --in-order-decoder --wishbone-memory added Dolu1990 2021-01-23 17:48:34 +0100
  • bdb5bc1180 fpu div implement some special values handeling Dolu1990 2021-01-22 20:47:31 +0100
  • 7d79685fe2 fpu mul now support special floats values and better rounding Dolu1990 2021-01-22 18:15:45 +0100
  • 4bd637cf88 fpu add now support special floats values and better rounding Dolu1990 2021-01-22 14:55:37 +0100
  • bcd140fc42 Add vexRiscvConfig.withMmu option Dolu1990 2021-01-21 13:28:04 +0100
  • ccd13b7e9e fpu zero/nan wip Dolu1990 2021-01-21 12:13:25 +0100
  • 50a69d8d4a
         Merge pull request #163 from lindemer/pmp-warl Dolu1990 2021-01-21 10:50:49 +0100
  • 6c13e6458f Remove registers storing PMP region bounds Samuel Lindemer 2021-01-20 14:16:10 +0100
  • ac5844f393 fpu add signed i2f/f2i Dolu1990 2021-01-20 13:15:29 +0100
  • 15d79ef330 fpu implement fclass and args for sub, fma, max, fcmp, fsgnj Dolu1990 2021-01-20 12:01:08 +0100
  • 828ea96006 PMP registers are now WARL Samuel Lindemer 2021-01-20 09:27:35 +0100
  • 11349a71fa fpu FpuPlugin now implement all instructions. Remains the FPuCore to implement cmd.arg and floating point corner cases Dolu1990 2021-01-19 17:57:41 +0100
  • 9f18045329 fpu add sstatus.fs Dolu1990 2021-01-19 16:06:16 +0100
  • a7d148d0ff fpu add vex csr Dolu1990 2021-01-19 15:53:11 +0100
  • f826a2ce51 fpu completion interface added + refractoring Dolu1990 2021-01-19 15:13:13 +0100
  • 8c4fae8bf2 fpu add min/sgnj/fmv Dolu1990 2021-01-19 13:27:42 +0100
  • ed68c8cf04
         Merge pull request #162 from lindemer/paging Dolu1990 2021-01-18 22:18:06 +0100
  • d7220031d4 fpu vex i2f works Dolu1990 2021-01-18 17:18:01 +0100
  • d4b877d415 fpu vex cmp/fle works Dolu1990 2021-01-18 15:09:30 +0100
  • 6cb498cdb2 fpu merge load/commit Dolu1990 2021-01-18 13:09:08 +0100
  • a9d8c0a19f fpu wip Dolu1990 2021-01-18 11:38:26 +0100
  • 3cda7c1f1b fpu wip Dolu1990 2021-01-15 14:03:37 +0100
  • 04499c0b76 FPU sqrt functional Dolu1990 2021-01-14 18:33:24 +0100
  • 85dd5dbf8e fpu div functional, sqrt wip Dolu1990 2021-01-14 15:56:56 +0100
  • 5e6c645461 Distinguish between page faults from MMU and access faults from PMP Samuel Lindemer 2021-01-14 08:34:54 +0100
  • 4ba7521af9 Access and page faults emitted correctly from MMU and PMP Samuel Lindemer 2021-01-13 18:15:12 +0100
  • 8761d0d9ee FpuCore can add/mul/fma/store/load Dolu1990 2021-01-13 18:28:26 +0100
  • d1fdcebba6 Rename exception generator flags to match specification Samuel Lindemer 2021-01-13 14:08:11 +0100
  • 6e0be6e18c Cfu add state index and cfu index Dolu1990 2021-01-11 13:43:57 +0100
  • 930bdf9dda DataCache increase syncPendingMax to 32 and use a sync queue instead of async one Dolu1990 2021-01-01 23:59:00 +0100
  • 780ad01ac0 Add AES-instruction support Dolu1990 2020-12-21 11:50:54 +0100
  • 0e2177ce49 Fix DBusSimplePlugin catchAccessFault for store operations. losfair 2020-12-15 15:25:09 +0800
  • d2855fcfca
         Merge pull request #147 from lindemer/pmp Dolu1990 2020-12-11 15:22:28 +0100
  • c59499ec03 typo Dolu1990 2020-12-11 14:13:33 +0100
  • eaff52b264 Add comments to the AesPlugin Dolu1990 2020-12-11 13:51:10 +0100
  • 6da09967f8 Add comments to the AesPlugin Dolu1990 2020-12-11 13:46:49 +0100
  • 7d699dcc13 Remove PMP from MachineOs test defaults Samuel Lindemer 2020-12-10 09:39:56 +0100
  • f2ce2eab00 PMP plugin passes regression tests Samuel Lindemer 2020-12-07 09:11:26 +0100
  • 763eebeeba Add TOR support, tests pass on GenZephyr Samuel Lindemer 2020-12-04 10:11:49 +0100
  • 5cb5061d9b PMP passes test with GenZephyr, but pipeline flushes have been disabled Samuel Lindemer 2020-12-03 17:29:31 +0100
  • 9a6931a54c CfuPlugin improve writeback buffering Dolu1990 2020-12-03 16:21:52 +0100
  • 987de8fb6a Lock PMP address registers in golden model Samuel Lindemer 2020-12-02 14:18:17 +0100
  • 14c39a0070 Merge remote-tracking branch 'upstream/master' into pmp Samuel Lindemer 2020-12-02 14:08:32 +0100
  • 872aa19d83 Add PMP to golden model Samuel Lindemer 2020-12-02 10:25:15 +0100
  • d5b1a8f565 Add PMP test to regression suite Samuel Lindemer 2020-12-01 18:35:51 +0100
  • 45ff78d068 VexRiscvSmpClusterGen.dBusCmdMasterPipe option added Dolu1990 2020-12-01 13:51:03 +0100
  • c5023ad973 Add PMP regression test Samuel Lindemer 2020-11-26 15:08:08 +0100
  • 1b65a9e523
         remove libts-dev from readme Dolu1990 2020-11-30 16:11:00 +0100