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371 Commits 5 Branches 14 Tags 5.7 MiB
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371 Commits

Author SHA1 Message Date
Florent Kermarrec 3b5a1ff906 modules: add K4B1G0446F 2018-10-08 17:36:32 +02:00
Florent Kermarrec 48c17ce8a4 modules: fix tWTR regression on MT46H32M32 2018-10-02 18:53:13 +02:00
Florent Kermarrec ad0a1d4215 modules: improve timings definition (keep retro-compatibility with previous definitions) 2018-10-02 10:32:45 +02:00
Florent Kermarrec 5b02791580 modules: add tCCD to all modules 2018-10-02 08:41:48 +02:00
Tim 'mithro' Ansell 6c7a804986 Adding tCCD for DDR2 modules. 2018-10-01 19:01:12 -07:00
208f5562d1 Merge branch 'master' of https://github.com/enjoy-digital/litedram 2018-10-01 19:36:05 -04:00
69eaf844e8 Fix DDR2 and below compilation failure 2018-10-01 19:35:20 -04:00
Florent Kermarrec 41a8a246b6 modules: express tFAW in ns 2018-10-01 19:41:30 +02:00
Florent Kermarrec 70620689a0 modules: split DDR3 in 2 categories: Chips and SO-DIMMs 2018-10-01 12:17:50 +02:00
Florent Kermarrec 0f46dc4ab7 modules: add DDR3-800 timings for MT41J128M16 and use it on arty example 2018-10-01 11:59:54 +02:00
Florent Kermarrec 426ae23d2a examples/litedram_gen: add sdram_module_speedgrade parameter 2018-10-01 11:48:15 +02:00
Florent Kermarrec 1bc016cf6c test: add test_examples 2018-10-01 11:29:08 +02:00
Florent Kermarrec f7f8169883 test: update downconverter/upconverter 2018-10-01 11:18:54 +02:00
Florent Kermarrec 8de1d91eac core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed) 2018-10-01 11:18:39 +02:00
70516c40bf Merge branch 'master' of https://github.com/enjoy-digital/litedram 2018-09-30 22:17:45 -04:00
Florent Kermarrec 58209708e7 frontend/crossbar: fix #49 2018-09-29 20:09:07 +02:00
71f78d953e Fix reordering controller rejecting all commands 2018-09-29 13:52:20 -04:00
8f14211f00 Account for CWL in write to read timing 2018-09-29 12:39:40 -04:00
Florent Kermarrec 5fb8afe7e5 frontend/axi: omit bank in rdata connect 2018-09-28 23:44:12 +02:00
enjoy-digital 06ca53d2b2
Merge pull request #48 from enjoy-digital/staging 
Staging
 2018-09-28 23:29:41 +02:00
enjoy-digital 5a4d063f64
Merge branch 'master' into staging 2018-09-28 23:29:24 +02:00
Florent Kermarrec 5984eaa6da core: change api for out-of-order. (with_reordering passed to controller and not ports). 
We are not going to mix in-order/out-of-order ports
 2018-09-28 23:16:54 +02:00
Florent Kermarrec 6e10daed58 core/bankmachine/write to precharge: indicate that AL=0 2018-09-25 21:04:19 +02:00
enjoy-digital 869c8ee618
Merge pull request #46 from enjoy-digital/WritePrechargeFix 
Update the write-to-precharge timings so it works with 1:2
 2018-09-25 20:59:36 +02:00
0405f4156d Update the write-to-precharge timings so it works with 1:2 2018-09-25 12:06:19 -04:00
Florent Kermarrec 30c32f557c example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :) 2018-09-25 10:40:24 +02:00
Florent Kermarrec 2a3cacb967 core/bankmachine: minor cleanup on trc/tras 2018-09-23 21:19:17 +02:00
enjoy-digital 42ccf05e15
Merge pull request #45 from enjoy-digital/tRAS_FIX 
Implement tRAS
 2018-09-23 22:19:58 +02:00
John Sully 79b1421878 Auto precharge is too pessimistic, it will wait on its own for a valid time to execute 2018-09-23 20:55:24 +02:00
John Sully 177d7393f9 Implement tRAS 2018-09-23 19:42:46 +02:00
enjoy-digital 59020270af
Merge pull request #44 from enjoy-digital/tRC_Fix 
This adds support for tRC timing parameters
 2018-09-23 18:09:15 +02:00
John Sully 5f6b85703d This adds support for tRC timing parameters 2018-09-23 17:56:07 +02:00
enjoy-digital 1777720a0c
Merge pull request #42 from enjoy-digital/HalfRateSequentialFix 
We wait an extra cycle for no reason
 2018-09-23 15:04:42 +02:00
John Sully 06c8c2afcf The actual fix 2018-09-23 11:32:49 +02:00
John Sully e22580f9bd remove unnecessary file 2018-09-23 11:22:25 +02:00
John Sully c028786702 Fix overflow bug from code review 2018-09-23 11:01:58 +02:00
enjoy-digital 04aa04d123
Merge pull request #43 from enjoy-digital/EfficencyFixes 
Bank valid/ready refactor
 2018-09-23 09:40:14 +02:00
John Sully 8447d69326 We wait an extra cycle for no reason 2018-09-23 01:29:19 +02:00
John Sully c4bd842cdf Fix many bugs 2018-09-23 01:21:18 +02:00
John Sully fa0f3b2777 Use the ready signal for cas_allowed so that arbitrators know not to iterate 2018-09-22 17:15:19 +02:00
Florent Kermarrec c12404e00c README: Add ECC 2018-09-19 11:42:13 +02:00
Florent Kermarrec 3f4c14b068 frontend/ecc: expose incident bits, change clear register name 2018-09-19 11:33:49 +02:00
Florent Kermarrec b9aadf11d1 frontend/axi: remove write buffer reservation (not needed) 2018-09-19 10:53:40 +02:00
Tim 'mithro' Ansell ea1ac4d6d7 s6ddrphy: Pass missing nranks parameter. 
Fixes #41.
 2018-09-18 16:58:07 -07:00
Florent Kermarrec e5696ad3ef frontend/ecc: add enable csr 2018-09-18 19:30:08 +02:00
Florent Kermarrec e6ef89a4d3 frontend/axi: optimize burst2beat timings 2018-09-18 19:15:40 +02:00
Florent Kermarrec 6941285d3f frontend/ecc: split Write/Read path and add buffer to improve timings 2018-09-18 17:23:18 +02:00
Florent Kermarrec 041817df7a frontend/ecc: use csr instead of signal for control 2018-09-18 16:23:54 +02:00
Florent Kermarrec b145b0c338 frontend/axi: fix write response implementation 2018-09-18 15:24:41 +02:00
Florent Kermarrec d23dbf6e57 phy: add nranks to all phys 2018-09-17 09:07:09 +02:00