93488009c9
test: rename test_timing_controllers to test_timing
2019-07-23 16:05:31 +02:00
8cf561d620
test/test_timing_controllers: add simple tFAWController tests
2019-07-23 15:58:26 +02:00
3ae666d015
test/test_timing_controllers: add simple tXXDController tests
2019-07-23 15:48:32 +02:00
394a49a759
test: add test_timing_controllers with tXXDController test
2019-07-23 12:40:40 +02:00
6e3f7691c5
core: move timing controllers to common
2019-07-23 12:39:14 +02:00
54cdc7f4cb
test: -x on tests
2019-07-23 12:16:44 +02:00
2ecb0534ec
frontend/ecc: move generic part of ECC to LiteX
2019-07-13 11:47:13 +02:00
8646b2e2c4
test/test_adaption: use same DUT for up/down converter tests
2019-07-13 10:52:41 +02:00
9f9fed02f6
test: merge test_downconverter/test_upconverter in a single test_adaptation file
2019-07-13 10:31:30 +02:00
fc41751080
frontend/dma: simplify rsv_level expose
2019-07-05 11:30:57 +02:00
88835de734
Merge pull request #86 from sergachev/master
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dma: expose reservation level in the reader
2019-07-05 11:29:26 +02:00
f145287fdc
dma: expose reservation level in the reader
2019-07-05 09:57:13 +02:00
f018c9e268
add CONTRIBUTORS file and add copyright header to all files.
2019-06-23 23:59:10 +02:00
18dda2db54
phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits
2019-06-22 10:46:02 +02:00
690e4f848f
README: fix ECP5 frequency ratio
2019-06-16 21:35:46 +02:00
67de3cee14
Merge pull request #85 from antmicro/fix_databits
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PhySettings: set missing databits parameter for S6QuarterRateDDRPHY
2019-06-13 16:55:11 +02:00
24851c9a3b
PhySettings: set missing databits parameter for S6QuarterRateDDRPHY
2019-06-13 15:41:47 +02:00
fef530366a
test: clean test_downconverter/test_upconverter (thanks sb0)
2019-06-13 09:15:09 +02:00
7fbe0b712c
Merge pull request #84 from open-design/is42s16320
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modules: SDRAM: add IS42S16320 support
2019-06-02 18:38:12 +02:00
5c66547334
modules: SDRAM: add IS42S16320 support
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The IS42S16320D-7TL 32Mx16 512Mb SDRAM chips
are used in Terasic DE1-SoC and Terasic DE2-115
FPGA development boards.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-01 15:05:58 +03:00
8e2df17747
modules: fix tRFC change on MT16KTF1G64HZ
2019-05-28 22:42:45 +02:00
bc88cfa6f7
modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 definitions (thanks @ambrop72 for the review)
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In some DDR3/DDR4 datasheet, tRFC is defined in ck or in ns. Allow definition in ck or ns
and review all the modules.
2019-05-28 10:17:39 +02:00
fbd7ae3e62
modules: make IS43TR16128B consistent with others SDRAMModules
2019-05-28 10:02:02 +02:00
02448a3670
Merge pull request #83 from ambrop72/IS43TR16128B_125K
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modules/ddr3: add IS43TR16128B_125K
2019-05-28 09:59:57 +02:00
d1089701d4
modules/ddr3: add IS43TR16128B_125K
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This is the chip that is actually on my Arty A7 100T (there is no mention of this chip in the Arty reference, which claims it is MT41K128M16JT-125).
2019-05-27 19:36:38 +02:00
da68e21bad
Merge pull request #82 from gsomlo/gls-expose-csr
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examples/litedram_gen: allow direct access to CSR (I/O) registers
2019-05-17 21:27:45 +02:00
65451f426a
examples/litedram_gen: allow direct access to CSR (I/O) registers
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
[florent@enjoy-digital.fr: use add_csr_master, fix csr_port.dat_r typo]
2019-05-16 15:05:30 -04:00
50e1d478db
PhySettings: add databits to allow SoC to compute memory size more easily
2019-05-10 15:44:44 +02:00
b93412bbdc
examples: remove verilog simulation
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Simulation was here just to show how to do system level simulation adn required
external component to work (stadalone init).
2019-05-10 13:05:48 +02:00
a7e46bb25c
example/litedram_gen: reserve_nmi_interrupt no longer exists
2019-05-10 12:43:23 +02:00
094fc2e736
Merge pull request #79 from gsomlo/gls-ulong-addr
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sdram_init: use "unsigned long" for address values
2019-05-01 12:08:44 +02:00
54d3312cc6
sdram_init: use "unsigned long" for address values
2019-04-29 15:00:13 -04:00
3caaa2eb13
common/tXXDController: revert Yosys workarounds
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Now fixed with https://github.com/YosysHQ/yosys/pull/850
2019-04-29 14:24:31 +02:00
44bbb93620
phy: add copyrights
2019-04-29 09:16:53 +02:00
6ddc2c83e4
README: update
2019-04-27 09:47:48 +02:00
9190a76741
travis: simplify and add RISC-V toolchain to run examples
2019-04-22 08:17:10 +02:00
e824288924
frontend/axi: move AXIBurst2Beat to LiteX
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Will be useful for others purposes.
2019-04-19 12:14:13 +02:00
be269da3fe
frontend/axi: use definitions from LiteX
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AXI definitions were not present in LiteX when AXI support was added to LiteDRAM.
2019-04-19 11:58:05 +02:00
e81b5a11b8
sdram_init: set __attribute__((unused)) on command_px to avoid compilation warning
2019-04-12 18:22:00 +02:00
c4161cfbfe
examples: update sim
2019-03-15 20:16:42 +01:00
201a0e2fb4
test/test_examples: add nexys4ddr
2019-03-15 20:10:50 +01:00
69afaf5a19
common: add separators, reorganize a bit
2019-03-15 20:08:08 +01:00
0bc241c2bf
phy/ecp5ddrphy: use inline comments on ECP5DDRPHYInit
2019-03-14 23:50:36 +01:00
c65ff974b6
phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers
2019-03-05 12:25:31 +01:00
4274db809e
common/TXXDcontroller: fix for compatibility with Yosys and vendor tools
2019-03-04 12:48:42 +01:00
a74d5c9d9e
common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value
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Fix SDRAM build with Yosys
2019-03-04 09:22:03 +01:00
cec35f3efd
Merge pull request #77 from daveshah1/ecp5_75MHz
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ecp5ddrphy: Shift read position forwards to fix higher frequencies
2019-03-02 22:34:12 +01:00
fa26dcdcb0
ecp5ddrphy: Shift read position forwards to fix higher frequencies
2019-03-02 19:14:14 +00:00
6715c1bd45
Merge pull request #76 from daveshah1/trellis_io
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ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs
2019-02-25 19:26:45 +01:00
691d9308b2
ecp5ddrphy: Use triples for inputs to fix build with TRELLIS_IOs
2019-02-25 18:03:05 +00:00
Florent Kermarrec
Ilia Sergachev
Mateusz Holenko
Antony Pavlov
Ambroz Bizjak
Gabriel L. Somlo
David Shah