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1206 Commits

Author SHA1 Message Date
Andrew Butt b4a2b7f9b0 Fix UpConverter reversed write mask 
Signed-off-by: Andrew Butt <andrewb1999@gmail.com>
 2021-04-27 02:08:31 -04:00
Florent Kermarrec 886f60d32c test/reference: Update. 2021-04-23 11:26:30 +02:00
Florent Kermarrec 6a80773bc8 init: Simplify SDRAM_PHY_MODULES define: this is just SDRAM_PHY_DATABITS/8. 2021-04-23 09:05:32 +02:00
Florent Kermarrec 103534d0e8 init: Enable DQ-DQS training on 7-Series (except Artix7) and Ultrascale. 2021-04-22 18:34:18 +02:00
Florent Kermarrec 3f4b6f661c init: Cleanup PHY lists in capabilities. 2021-04-22 17:38:14 +02:00
enjoy-digital fda8689142
Merge pull request #244 from antmicro/jboc/dq-dqs-training 
Add DQ-DQS training for LPDDR4 PHY
 2021-04-22 17:28:10 +02:00
Florent Kermarrec 6256031d51 bench: Update build directories and add rst in CRG (triggered on CPU reboot). 2021-04-22 14:57:13 +02:00
Florent Kermarrec c2a779df46 bench: Update test targets (add_csr no longer required). 2021-04-19 13:40:17 +02:00
Jędrzej Boczar ebaf63479d init/lpddr4: modify pull-down drive strength to improve signal quality 2021-04-16 15:35:35 +02:00
Jędrzej Boczar 98f2f24e20 init: enable DQ-DQS training for LPDDR4 PHYs with output delays 2021-04-16 15:12:44 +02:00
enjoy-digital 26c9f82c1b
Merge pull request #236 from jersey99/master 
modules.py: Add MT41J256M8 (Passes mem_test on HW @ sys4x=500MHz, vex…
 2021-04-01 19:00:51 +02:00
enjoy-digital e898507409
Merge pull request #242 from antmicro/jboc/lpddr4-copyrights 
lpddr4: add missing copyright comments
 2021-04-01 19:00:15 +02:00
enjoy-digital 172add8dfc
Merge pull request #240 from antmicro/jboc/lpddr4 
lpddr4: add a local README with a summary of the code
 2021-04-01 18:54:42 +02:00
enjoy-digital 478157560f
Merge pull request #241 from antmicro/jboc/lpddr4-init-fix 
Fix Python header generation for LPDDR4
 2021-04-01 18:53:38 +02:00
Jędrzej Boczar 7028944acd lpddr4: add missing copyright comments 2021-04-01 10:07:02 +02:00
Jędrzej Boczar c12e832bcb init: fix python header generation 
With the previous code lines included python variable names instead of integers, e.g.
("ZQ Calibration start", MPC.ZQC_START, SpecialCmd.MPC, dfii_command_we|dfii_command_cs, 200)
which failed as these names were not being imported.
 2021-03-31 15:58:43 +02:00
Jędrzej Boczar 13db84ceb5 lpddr4: add a local README with a summary of the code 2021-03-31 12:51:34 +02:00
enjoy-digital 996d0add26
Merge pull request #224 from antmicro/jboc/lpddr4 
Add LPDDR4 PHY
 2021-03-31 09:35:06 +02:00
enjoy-digital f5e7c39776
Merge pull request #238 from antmicro/jboc/refresh-all-banks 
core/refresher: use A10=1 for an all-banks REF
 2021-03-31 08:50:25 +02:00
enjoy-digital df2a06584b
Merge pull request #237 from antmicro/jboc/dfii-bankbits 
core: use wider DFI address/bank if PHY requires it
 2021-03-31 08:48:32 +02:00
Florent Kermarrec 04334ae141 phy/s7ddrphy/usddrphy: Use explicit sys clock domain on ClockSignal/ResetSignal. 
Improve readability.
 2021-03-30 08:51:44 +02:00
Florent Kermarrec 5cd192a708 bench: Remove soc_sdram import (No longer useful and deprecated). 2021-03-30 08:49:54 +02:00
Jędrzej Boczar 06b30979dd lpddr4/s7phy: add with_odelay parameter and Artix/Kintex/Virtex variants 2021-03-25 15:31:58 +01:00
Jędrzej Boczar e07198ac57 lpddr4/utils: simplify ConstBitSlip 2021-03-25 15:31:58 +01:00
Jędrzej Boczar e860d86f3f lpddr4/phy: make redundant cmd overlaps checks optional (and disabled by default) 2021-03-25 15:31:58 +01:00
Jędrzej Boczar f282d809d1 lpddr4: remove old fixme comments 2021-03-25 15:31:58 +01:00
Jędrzej Boczar a64cb58753 core/refresher: use A10=1 for all banks REF 
This is needed because newer DRAMs like LPDDR4 or DDR5 have
separate commands for per-bank refresh and all banks refresh.
Other DRAM types ignore address for REF commands.
 2021-03-25 15:31:58 +01:00
Jędrzej Boczar a21b70e061 init: revert bitslips changed to 16 for phys other than S7LPDDR4PHY 2021-03-25 15:31:58 +01:00
Jędrzej Boczar f3a0a7d038 lpddr4/s7phy: remove OE delay CSRs, use fixed, tested values 2021-03-25 15:31:58 +01:00
Jędrzej Boczar ba57791c1d lpddr4/s7phy: extend time of holding output enable on tristate lines 2021-03-25 15:31:58 +01:00
Jędrzej Boczar 58235f478e lpddr4/init: increase CA/DQ Vref to 30.4% (yields better results) 2021-03-25 15:31:58 +01:00
Jędrzej Boczar 693695f067 lpddr4/init: initialize all More Registers (even if setting defaults) 2021-03-25 15:31:58 +01:00
Jędrzej Boczar 0ecb1340f5 lpddr4/test: fixes: use 2tCK write preamble, update read latency 2021-03-25 15:31:05 +01:00
Jędrzej Boczar 5c6796b92a lpddr4: change MRW command encoding to avoid changing BIOS code 2021-03-25 15:30:48 +01:00
Jędrzej Boczar f1a40cef2f core: use wider DFI address/bank if PHY requires it 2021-03-25 15:29:32 +01:00
Jędrzej Boczar eb1d900c24 lpddr4: S7PHY related fixes, MRR command, runtime configurable WRITE/MASKED-WRITE 2021-03-25 15:29:17 +01:00
Jędrzej Boczar 052dc19246 lpddr4: improve documentation 2021-03-25 15:21:01 +01:00
Jędrzej Boczar 1b65e858b3 lpddr4/utils: rework `once` helper function to be more generic 2021-03-25 15:21:01 +01:00
Jędrzej Boczar 4473335954 lpddr4/commands: replace MPC dict with an enum with docstring 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 7f19e92c75 ci: add dependencies required for Verilator-based tests 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 4415a3eaf5 lpddr4: improve simulation and Verilator tests runner 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 4a5feb9e11 lpddr4/s7phy: improve to use the new DoubleRateLPDDR4PHY 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 2ab763ac5e lpddr4: add double-rate PHY, clean up and improve PHY implementation 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 183f1643aa lpddr4: add support for MASKED-WRITE 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 4b78fc99e8 lpddr4/sim: create LPDDR4 simulator and Verilator target 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 05ed238829 lpddr4: split implementation into multiple files in separate directory 2021-03-25 15:19:16 +01:00
Jędrzej Boczar ee9c2b4cf7 lpddr4: implement ZQC through MPC and include it in init sequence 
We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 055e2dc597 lpddr4: add initial PHY for Series7 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 4d9106847f init: add LPDDR4 initialization 2021-03-25 15:19:16 +01:00
Jędrzej Boczar 788b3f6d02 modules: modules: add LPDDR4 module 2021-03-25 15:19:16 +01:00