59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
da61aabc5b
targets: remove USDDRPHY_DEBUG and set cmd_latency to on all Kintex7/Ultrascale targets.
2020-05-05 16:32:10 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
84468c2a63
targets/CRG: platforms are now automatically constraining the input clocks.
2020-05-05 11:51:57 +02:00
1f88a9d5ec
platforms: make sure clocks inputs are constraints on all platforms.
...
Also use new loose lookup_request to simplify constraints.
2020-05-05 11:45:41 +02:00
78b5727774
targets: rename usb_cdc to usb_acm.
...
As discussed recently on Discord.
2020-04-30 21:48:10 +02:00
2213d73b89
targets/kcu105: use cmd_latency=1.
2020-04-25 12:13:49 +02:00
a8a42c55c9
targets/kc705: manual DDRPHY_CMD_DELAY adjustment no longer needed.
2020-04-25 11:08:05 +02:00
865b01ec75
ecpix5: add ethernet.
2020-04-22 20:21:59 +02:00
6fe4c4ea62
ecpix5: add DDR3 (working)
2020-04-22 17:03:22 +02:00
efb13bc118
add mininal ECPIX-5 board support (Clk/Rst/Leds/UART), BIOS working.
2020-04-22 16:31:07 +02:00
4154bdf034
targets/PCIe: add PCIe software reset.
2020-04-20 12:30:09 +02:00
4185a019f5
targets: manual define of the SDRAM PHY is no longer needed.
2020-04-16 11:25:59 +02:00
cb95962850
targets/ulx3s and colorlight_5a_75b: cleanup USB ACM addition and only keep USB ACM changes.
...
- remove update in loading/flashing: we need to thinks how to integrate this.
- remove specific README: documentation is moved to the files, link to more complete project can
be added if maintained externally, as done for the iCEBreaker for example.
- revert default freq on ULX3S to 50MHz and instantiate a second PLL as done on the colorlight.
2020-04-14 16:14:18 +02:00
f79a010a29
Addition of flash for colorlight board
2020-04-14 14:37:56 +01:00
389e8aa13a
Addition of USB ACM for ECP5
2020-04-14 13:53:46 +01:00
a12faae0fb
targets/colorlight_5a_75b: increase sys_ps phase (fixes memtest).
2020-04-14 11:24:16 +02:00
52c9648176
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
2020-04-13 15:20:36 +02:00
bbb1ded9f8
Added Arty S7 board
...
As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.
2020-04-12 21:48:25 +02:00
188d4a45d6
targets: use DDROutput on sdram_clock and similar configuration for all SDRAM targets.
2020-04-10 14:43:04 +02:00
ca197af2be
targets/simple: use CRG from litex.build.
2020-04-10 10:26:19 +02:00
b8a648d499
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:23:33 +02:00
467b14a0ad
colorlight_5a_75b: minor comment changes.
2020-04-09 08:14:17 +02:00
15a27d40fa
targets/colorlight_5a_75b: Change baudrate to work on v6.1
...
There seems to be some capacitance on KEY+, so the usual 115200 don't work
2020-04-09 05:08:23 +02:00
db67dff0ea
targets/de10lite: use Max10PLL, remove 50MHz limitation.
2020-04-08 08:55:30 +02:00
8ccab03358
targets/c10lprefkit: use Cyclone10LPPLL, remove 50MHz limitation.
2020-04-08 08:34:59 +02:00
4cdc121327
targets/de10nano: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:11:04 +02:00
2d8a4ef9ec
targets/de1_soc: use CycloneVPLL, remove 50MHz limitation.
2020-04-08 08:07:37 +02:00
cec4cbb6dc
targets/de2_115: use CycloneIVPLL, remove 50MHz limitation.
2020-04-08 08:03:41 +02:00
1fac6077fb
targets/de0nano: use CycloneIVPLL, remove 50MHz limitation.
2020-04-07 17:01:58 +02:00
5f629c203b
targets/vcu118: fix clk500 typo.
2020-04-07 13:53:22 +02:00
a7fbe0a724
colorlight_5a_75b: add SoC with regular UART (on J19).
2020-04-03 10:28:53 +02:00
19e5366ad1
targets/colorlight_5a_75b: update sys/sys_ps phases.
2020-03-31 18:18:45 +02:00
d2edf54ab3
zcu104: add fully working SO-DIMM config
2020-03-26 16:37:11 +01:00
3b91e96c42
targets/add_constant: avoid specifying value when value is None (=default)
2020-03-26 09:47:22 +01:00
555bf6c4dc
targets/Ultrascale(+): enable USDDRPHY_DEBUG.
2020-03-26 09:17:09 +01:00
4053c02d7e
targets/orangecrab: add USB PLL for USB CDC with ValentyUSB.
2020-03-25 19:38:36 +01:00
85f38876c2
targets: update PCIe on Numato targets.
...
Should be compatible with software from: https://github.com/enjoy-digital/netv2 .
2020-03-25 11:53:52 +01:00
24033e331c
targets: update SDRAM to use new GENSDRPHY and new ECP5PLL phase support.
2020-03-24 19:59:42 +01:00
eb35ec92ba
orangecrab: combine revisions in target
2020-03-23 09:20:01 +10:30
159360da2c
orangecrab: Add r0.2 support
2020-03-22 21:04:07 +10:30
bf3c9dc9bf
orangecrab: Add sdram selection option
2020-03-22 20:41:12 +10:30
88d3f1d63e
orangecrab: r0.1 OrangeCrab fixes
2020-03-22 20:14:29 +10:30
78224b1e56
targets/colorlight_5a_75b: add SDRAM.
2020-03-21 22:11:47 +01:00
a95a4eed3f
targets/colorlight_5a_75b: switch to add_ethernet/add_etherbone methods.
2020-03-21 21:50:05 +01:00
7bba5caab0
targets/c10prefkit: remove keep attributes (no longer needed, added automatically).
2020-03-21 21:44:44 +01:00
6c31933e89
targets: switch to add_etherbone method.
2020-03-21 21:40:45 +01:00
159386e3d3
targets: always use sys_clk_freq on SDRAM modules.
2020-03-21 20:00:56 +01:00
3fb3ba18e8
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-21 18:29:52 +01:00
Florent Kermarrec
Dave Marples
Staf Verhaegen
David Sawatzke
Piotr Binkowski
Greg Davill