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979 commits

Author SHA1 Message Date
Florent Kermarrec
a4d178a740 Add Efinix Trio T120 BGA576 Dev-Kit initial support (LedChaser). 2021-10-13 12:29:53 +02:00
Florent Kermarrec
83e64fbd64 targets/qmtech_10cl006: +x. 2021-10-13 12:16:41 +02:00
Florent Kermarrec
e29bcd30a6 litex_acorn_baseboard: Add some M2 signals and set devslp to 0. 2021-10-12 11:54:17 +02:00
Florent Kermarrec
a365362f5d Rename litex_m2_baseboard to litex_acorn_baseboard and add link to repository. 2021-10-11 18:36:12 +02:00
Florent Kermarrec
fe08491e8d litex_m2_baseboard: Add LCD. 2021-10-11 18:30:23 +02:00
enjoy-digital
393252ddc9
Merge pull request #277 from hansfbaier/master 
Add support for QMTech 10CL006 board
 2021-10-11 14:01:06 +02:00
enjoy-digital
79fe4a9199
Merge pull request #275 from alainlou/master 
rz_easyfpga: cleanup and ease of use
 2021-10-11 13:57:06 +02:00
Florent Kermarrec
2b2c7d3d68 trellisboard: Add PMOD GPIO support (for tests with MicroPython). 2021-10-11 11:33:13 +02:00
Florent Kermarrec
9e18d9bc34 gsd_butterstick: Remove ECLKBRIDGECS (not required). 2021-10-07 14:09:22 +02:00
Hans Baier
d119b598c5 Add support for QMTech 10CL006 board 2021-10-05 12:06:41 +07:00
alainlou
1b676f929a cleanup and ease of use 
- update README
- delete some unnecessary toolchain commands (copied from trenz boards)
- use minimal cpu_variant by default when vexriscv is selected
 2021-10-03 13:21:45 -04:00
Florent Kermarrec
e8611794b4 Add initial QuickLogic QuickFeather support (Led Chaser). 
Untested.
 2021-10-01 10:58:26 +02:00
Florent Kermarrec
de4ad324cb mnt_rkx7: Revert default sys_clk_freq to 100MHz. 2021-09-30 18:03:22 +02:00
Florent Kermarrec
1858273945 mnt_rkx7: Add SPI SDCard support. 2021-09-30 18:01:54 +02:00
Florent Kermarrec
05f3158311 mnt_rkx7: Increase default sys_clk_freq to 125MHz. 2021-09-30 16:22:18 +02:00
Florent Kermarrec
1217e94218 mnt_rkx7: Switch DDR3 to IS43TR16512B now added to LiteDRAM. 2021-09-30 15:45:40 +02:00
Florent Kermarrec
9bcae49629 mnt_rkx7: Add I2C (For the SiI9022A). 2021-09-30 15:33:53 +02:00
Florent Kermarrec
4f7c18a503 mnt_rkx7: Add Ethernet/Etherbone support. 2021-09-30 15:14:03 +02:00
Florent Kermarrec
84f0d715ff mnt_rkx7: Add SDCard support. 2021-09-30 11:34:23 +02:00
Florent Kermarrec
31b404c42f mng_rkx7: Add SPI Flash support. 2021-09-30 11:29:56 +02:00
Florent Kermarrec
df7fe5687e Add initial MNT Reform Kintex-7 module (RKX7) support with Clk, UART and DDR3. 
Compiles but untested on hardware.
 2021-09-30 11:06:39 +02:00
Florent Kermarrec
82653cf66f icebreaker/fomu: Fix SPRAM split. 2021-09-30 09:32:26 +02:00
Florent Kermarrec
5addd7f7d8 icebreaker/fomu: Split PSRAM in half: 64kB SRAM/64kB RAM). 
Allows building bare metal demo and running it directly on these boards.
 2021-09-29 19:33:22 +02:00
enjoy-digital
dfa572083a
Merge pull request #273 from ozbenh/wukong-v2 
Wukong board improvements
 2021-09-28 13:22:42 +02:00
Alessandro Comodi
228245075a boards: added datacenter DDR4 RDIMM tester board 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-27 10:15:55 +02:00
Benjamin Herrenschmidt
4a52996106 Wukong board improvements 
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.

Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.

This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2021-09-24 12:13:56 +10:00
enjoy-digital
f18b10d1ed
Merge pull request #249 from Quiddle11/atlys 
Initial Digilent Atlys support
 2021-09-23 10:21:49 +02:00
Florent Kermarrec
921c300b50 digilent_atlys: Simplify/Remove entropy... 
Build tested with ./digilent_atlys.py --with-ethernet --build.
 2021-09-23 10:17:54 +02:00
alainlou
1333f89ed6 rz_easyfpga: adjust SDRAM clk phase 
- also add 1:2 rate
 2021-09-22 00:26:28 -04:00
Alain Lou
610e82d774
Add initial RZ-EasyFPGA support! (#270) 2021-09-21 09:55:22 +02:00
Florent Kermarrec
d5eea94289 sispeed_tang_nano_4k: Avoid IOStandard constraints on HyperRAM (Not present in example designs). 2021-09-20 11:46:10 +02:00
Florent Kermarrec
5190c9c869 sipeed_tang_nano_4k: Initial Video Out support. 
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
 2021-09-20 09:32:20 +02:00
Florent Kermarrec
30756ce05e targets: Update to VideoHDMIPHY. 2021-09-20 09:30:32 +02:00
Florent Kermarrec
7161ad18ec sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL. 2021-09-20 08:40:19 +02:00
Florent Kermarrec
a5c5ba7652 sipeed_tang_nano_4k: Integrate HyperRam (not yet working). 2021-09-17 16:30:39 +02:00
Florent Kermarrec
376a836583 sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader. 
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-09-17 15:57:55 +02:00
Florent Kermarrec
28571308bc sispeed_tang_nano: Add simple UART loopback test... (Not working...) 2021-09-16 19:34:48 +02:00
Florent Kermarrec
5955a35372 Add initial Sipeed Tang Nano support (Clk/Leds/Buttons). 2021-09-16 19:22:30 +02:00
Florent Kermarrec
c0aed8a727 litex_m2_baseboard: Add Video Terminal support. 2021-09-16 18:54:50 +02:00
Florent Kermarrec
32a9256f3b litex_m2_baseboard: Add SDCard support. 2021-09-16 18:17:34 +02:00
Florent Kermarrec
0854a5d234 litex_m2_baseboard: Add Ethernet/Etherbone support. 2021-09-16 18:02:55 +02:00
Florent Kermarrec
8d2f75ca6d litex_m2_baseboard: Add PMODs connectors. 2021-09-16 17:48:53 +02:00
Florent Kermarrec
3ad0eb6992 Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons. 2021-09-16 17:44:50 +02:00
enjoy-digital
26943959b5
Merge pull request #268 from trabucayre/runber_support 
Add runber support
 2021-09-15 08:32:05 +02:00
Gwenhael Goavec-Merou
7ccae3332d Add runber support 2021-09-15 06:50:57 +02:00
Gwenhael Goavec-Merou
fed36afaba platforms/sipeed_tang_nano_4k: fix period computation 2021-09-15 06:46:29 +02:00
Florent Kermarrec
68fb163a27 targets: Remove spiflash mapping on targets where it's no longer useful. 2021-09-14 18:35:13 +02:00
Florent Kermarrec
db91eda899 linsn_rv901t.py: Update Ethernet and add Etherbone support. 2021-09-13 19:35:05 +02:00
Nathaniel R. Lewis
b8373a361d alchitry_mojo: new board 2021-09-10 02:40:31 -07:00
enjoy-digital
d4613562a8
Merge pull request #265 from trabucayre/tangNano4K_connector 
platforms/sipeed_tang_nano_4k: add P6 and P7 connectors
 2021-09-09 11:43:05 +02:00
enjoy-digital
cacb76450f
Merge pull request #264 from teknoman117/alchitry-au 
Add Alchitry Au as new board
 2021-09-09 11:42:37 +02:00
Gwenhael Goavec-Merou
945e48ea83 platforms/sipeed_tang_nano_4k: add P6 and P7 connectors 2021-09-09 11:35:14 +02:00
Florent Kermarrec
8d91489756 tang_nano_4k: Add more IOs. 2021-09-09 11:23:20 +02:00
Nathaniel R. Lewis
9bbdb87130 alchitry_au: new board 2021-09-09 00:03:19 -07:00
Florent Kermarrec
88534c6689 tang_nano_4k: Fix typo in sipeed. 2021-09-08 23:02:39 +02:00
Florent Kermarrec
ce52c8c5ed beaglewire: Fix typo in qwertyembedded. 2021-09-08 21:29:29 +02:00
Florent Kermarrec
ecebe7e267 Add initial SiSpeed Tang Nano 4K support (Led blink only for now...). 
./sispeed_tang_nano_4k.py --build --load

Build with Gowin EDA.
Load with OpenFPGALoader.
 2021-09-08 19:36:46 +02:00
Florent Kermarrec
129b95f9b5 sqrl_acorn: Update pre_placement_commands with new XilinxVivadCommands. 2021-09-08 16:27:30 +02:00
Florent Kermarrec
7fa22a494b arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2). 
On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
 2021-09-07 15:07:59 +02:00
Florent Kermarrec
aa2209729f gsd_butterstick: Force uart_name to crossover when set to serial. 2021-09-02 15:23:05 +02:00
Florent Kermarrec
fddca1cd40 gsd_butterstick: Add SDCard (SPI & SD modes) support. 2021-09-02 14:06:09 +02:00
Florent Kermarrec
596f430326 gsd_butterstick: Add SPI Flash support. 2021-09-02 11:28:21 +02:00
Florent Kermarrec
1bbbf5b3e7 gsd_butterstick: Add SYZYGY0/1 IOs to connectors. 2021-09-02 10:26:18 +02:00
Florent Kermarrec
55ea71bd01 gsd_butterstick: Add initial DDR3 support. 
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge


        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep  1 2021 19:09:52
 BIOS CRC passed (3d349845)

 Migen git sha1: 27dbf03
 LiteX git sha1: 315fbe18

--=============== SoC ==================--
CPU:		VexRiscv @ 75MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |01110000| delays: 02+-01
  m0, b01: |00000000| delays: -
  m0, b02: |00000000| delays: -
  m0, b03: |00000000| delays: -
  best: m0, b00 delays: 02+-01
  m1, b00: |01110000| delays: 02+-01
  m1, b01: |00000000| delays: -
  m1, b02: |00000000| delays: -
  m1, b03: |00000000| delays: -
  best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 13.6MiB/s
   Read speed: 15.6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-09-01 19:21:16 +02:00
Florent Kermarrec
1f25a98476 butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone). 2021-09-01 18:03:13 +02:00
Florent Kermarrec
1f149ece6b Add intial ButterStick support (with just Clk, Buttons and Leds). 2021-09-01 17:33:54 +02:00
Dan Callaghan
74c2178150 lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL 
Setting MASTER_SPI_PORT=SERIAL causes the SPI flash pins to be reserved
for use by the sysCONFIG logic, and prevents user logic from assigning
them. This made it impossible to have a Litex design which accesses the
SPI flash on this board.

Remove the setting, so that we get the default behaviour which permits
user logic to assign these pins. In the unlikely event that someone
needs the pins to stay reserved for sysCONFIG after configuration (I'm
not sure why this would be needed) they could explicitly add this
command in their design.
 2021-09-01 18:47:17 +10:00
enjoy-digital
4731c500fb
Merge pull request #258 from danc86/clnexevn-device-arg 
lattice_crosslink_nx_evn: allow specifying the FPGA device
 2021-09-01 10:22:42 +02:00
Florent Kermarrec
ce254208ff beaglewire: Review/Cleanup for consistency with other targets. 
- Now uses regular UART.
- Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build
- Can still be build with Crossover UART with --uart-name=crossover+bridge.
 2021-09-01 10:18:11 +02:00
Florent Kermarrec
35df77258a beaglewire: Rename to quertyembedded_beaglewire. 2021-09-01 09:36:09 +02:00
enjoy-digital
1e1f6a476d
Merge pull request #254 from ombhilare999/master 
beaglewire platform and target added
 2021-09-01 09:33:07 +02:00
Florent Kermarrec
4a18951651 tul_pynq_z2: Fix copyrights, remove PS7 part for now. 2021-09-01 08:50:56 +02:00
enjoy-digital
54c777a49c
Merge pull request #252 from developandplay/PYNQ-Z2 
WIP: Initial PYNQ Z2 support
 2021-09-01 08:46:44 +02:00
enjoy-digital
6a08a7973c
Merge pull request #251 from niw/fix_orangecrab_feather_spi_pad_name 
FIX: OrangeCrab Feather SPI pad name
 2021-08-31 18:59:09 +02:00
Florent Kermarrec
8f1c15bdb8 ebaz4205: Remove PS7 support for now (since untested and we'll avoid the .xci in LiteX-Boards repository). 2021-08-31 18:56:47 +02:00
Dhiru Kholia
781d83bab6 Add support for EBAZ4205 'Development' Board 
Usage:

```
./ebaz4205.py --cpu-type=vexriscv --build --load
```

```
$ pwd
litex-boards/litex_boards/targets
```

Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.

References:

- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example

Note: The `PS7` stuff remains untested via LiteX for now.
 2021-08-31 18:54:49 +02:00
Yoshimasa Niwa
fc78c96444 FIX: OrangeCrab Feather SPI pad name 
**Problems**

`SPIMaster` pad names are `clk`, `cs_n`, `mosi`, and `miso`.
However, `feather_spi` is using `sck` instead of `clk`, therefore
it is not able to use as-is for `SPIMaster`, for example,
with `add_spi` on Linux On LiteX VexRiscv.

**Solution**

In fact, `spisdcard` and other SPI related pad names are
using `clk`, only `feather_spi` is using `sck`.
Therefore, rename `sck` to `clk`.
 2021-08-29 17:59:45 -07:00
Florent Kermarrec
b017a33f2b targets: Fix SPI Flash mapping on target supporting --with-spi-flash. 2021-08-23 18:05:40 +02:00
Dan Callaghan
cc9e39286a lattice_crosslink_nx_evn: allow specifying the FPGA device 
This board is documented as having the LIFCL-40-9BG400C part, but some
versions of the board exist which were fitted with LIFCL-40-8BG400CES,
an engineering sample part. The distinction is important because the
engineering sample requires a different device ID to be embedded in the
bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load
it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red
"INITN" LED on this board).

Accept --device to allow the user to specify which FPGA part their board
has.
 2021-08-17 18:30:03 +10:00
ombhilare999
db9c98b28a beaglewire platform and target added 2021-08-16 20:14:45 +05:30
Martin Troiber
22e823d756 Initial PYNQ Z2 support 2021-08-13 16:23:39 +02:00
enjoy-digital
b77b1514ce
Merge pull request #250 from david-sawatzke/fullmemwe 
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
 2021-08-11 09:53:47 +02:00
David Sawatzke
9f5e8d4864 colorlight_5a_75x: Disable full_memory_we for l2 cache by default 
Leads to an increase in DP16KD, first noticed in
https://github.com/enjoy-digital/liteeth/issues/70.
With full_mem_we:
```
Info: 	              DP16KD:    41/   56    73%
```
Without:
```
Info: 	              DP16KD:    29/   56    51%
```
 2021-08-08 14:37:46 +02:00
MV
b81309401e Initial Digilent Atlys support 2021-08-06 13:24:19 +02:00
Florent Kermarrec
615b97e205 tinyfpga_bx: Switch to LiteSPI. 2021-07-30 08:18:15 +02:00
Florent Kermarrec
90fcaec287 targets/radiona_ulx3s: Switch to LiteSPI. 2021-07-30 08:10:52 +02:00
Florent Kermarrec
fdf94b95c9 muselabe_icesugar/SPIFlash: Disable Master (to avoid wasting resources on this small FPGA). 2021-07-29 19:59:22 +02:00
Florent Kermarrec
218e830fbf muselab_icesugar_pro: Switch to LiteSPI. 2021-07-29 19:58:13 +02:00
Florent Kermarrec
569c20ab86 muselab_icesugar: Switch to LiteSPI. 2021-07-29 19:55:32 +02:00
Florent Kermarrec
8df797c716 lattice_ice40up5k_evn: Switch to LiteSPI. 2021-07-29 19:50:36 +02:00
Florent Kermarrec
5e8c29d657 colorlight_i5: Switch to LiteSPI. 2021-07-29 19:47:41 +02:00
Florent Kermarrec
35ba3d9bc3 targets: Remove old call to add_spi_flash on targets now using LiteSPI (we'll find it with gitk is required). 2021-07-29 11:55:10 +02:00
Florent Kermarrec
54cee05986 #248: Minor cleanup. 2021-07-28 18:20:42 +02:00
enjoy-digital
a41fbea5e6
Merge pull request #248 from JosephBushagour/jbushagour_fomu_spi_options 
Add option for different Fomu SPI ICs.
 2021-07-28 18:18:12 +02:00
Sergiu Mosanu
99ff82c75a xilinx_alveo_u280: Add more IOs and enable HBM2. 2021-07-28 18:11:49 +02:00
Joey Bushagour
7b3dce65c1 Add option for different Fomu SPI chips. 
Signed-off-by: Joey Bushagour <jbushagour@google.com>
 2021-07-28 10:34:02 -05:00
Florent Kermarrec
401568c54e digilent_arty_s7: Add SPI Flash. 2021-07-28 14:22:26 +02:00
Florent Kermarrec
64eadd8012 hackaday_hadbadge: Lower PLL's PFD Min from 10MHz to 8MHz. 
This is now required since ECP5PLL now checks that PFD is in required range.
 2021-07-28 12:25:17 +02:00
Florent Kermarrec
6ce5db1b90 qmtech_xc7a35t: Fix default build. 2021-07-28 12:23:24 +02:00
Florent Kermarrec
1f4383475a decklink_intensity_pro_4k: Fix default build. 2021-07-28 12:23:12 +02:00