76ac4a69a8
rename forest_kitten_33 platform/target to fk33.
2020-09-04 20:05:18 +02:00
979fee7517
forest_kitten_33: add pcie.
2020-09-04 20:02:43 +02:00
ad48728160
xcu1525: update headers (were still using old format).
2020-09-04 19:59:09 +02:00
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie
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alveo_u250: Add PCIe x4 support
2020-09-04 19:22:48 +02:00
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0
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Add support for 5A-75E V6.0 board
2020-09-04 19:21:02 +02:00
ae6a052e57
alveo_u250: Add PCIe x4 support
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Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
51e881d1ff
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
2020-09-03 19:06:43 +02:00
cc78574297
targets/colorlight_5a_75x: fix rx_data pin order for Ethernet PHY 0
2020-09-02 22:04:23 +02:00
8b1fee0e66
Add support for 5A-75E V6.0 board
2020-09-01 17:02:17 +02:00
beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
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- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
795e34aafd
add initial Crosslink-NX support.
2020-08-24 16:47:38 +02:00
70594a5305
ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.
2020-08-24 09:05:58 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
83d8b8d1b4
platforms/acorn_cle_215: integrated sdcard ios as extension.
2020-08-22 22:11:51 +02:00
f328909578
Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header.
2020-08-09 16:27:41 -04:00
d2cd6d4c0e
arty: Change USB-uart and I2S Pmod configuration
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This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board ).
2020-08-05 11:54:25 +02:00
eba70377b7
add optional OLED peripheral to ULX3S target
2020-08-04 11:07:30 +02:00
929e55d7e6
platforms/trellisboard: add SDCard PMOD pins.
2020-07-29 09:07:55 +02:00
5fd3e8dbcd
ecpix5: add SDCard.
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Validated with Linux-on-LiteX-VexRiscv.
2020-07-28 17:45:49 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
9730c6f722
platforms/de10nano: use additional sdram constraints required for HalfRate.
2020-07-24 12:27:36 +02:00
7399d13cef
paltforms/de10nano/sdram: enable fast input/output on dq.
2020-07-24 11:27:25 +02:00
b4b1ab8621
paltforms/de10nano: simplify IO constraints (for consistency with others platforms).
2020-07-24 09:03:35 +02:00
89c5bf43cf
Merge pull request #92 from rob-ng15/master
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Enable use of HalfRateGENSDRPHY on de10nano
2020-07-24 08:49:09 +02:00
1e1589a514
zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).
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This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
2020-07-23 17:45:21 +02:00
cf9839307f
Add Misc
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Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram
2020-07-23 14:40:04 +01:00
8a3b453e2f
add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB.
2020-07-23 15:26:22 +02:00
e723bef49a
platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope).
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Also use pmod connector names in i2s_pmod and sdcard_pmod.
2020-07-22 14:41:09 +02:00
19d0b95867
platforms/targets: keep in sync with litex.
2020-07-22 08:53:49 +02:00
0ee4b215b9
trellisboard/ulx3s: fix sdcard slewrate.
2020-07-21 15:23:08 +02:00
7efa1c37a1
platforms/arty: add missing pullups on sdcard.
2020-07-21 15:22:39 +02:00
2ce24df76d
platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3).
2020-07-18 22:18:41 +02:00
135c387155
platforms/ulx3s: add assertion for supported devices.
2020-07-17 12:04:06 +02:00
851378f0a9
platforms/trellisboard: move ddram_vtt_en.
2020-07-17 12:03:37 +02:00
44ad902aad
platforms/kc705.py: LPC DP0_M2C/C2M diff pair
2020-07-13 10:26:17 -07:00
a461f5ac59
orangecrab: add usb, rst_n signals for r0.1
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- fix standard io extensions
- Use newly assigned code for orangecrab 1209:5af0
2020-07-09 19:56:32 +09:30
f3d02d8fca
Merge pull request #87 from antmicro/arty_i2s
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arty: Add configuration of I2S pins
2020-07-07 17:22:10 +02:00
df54b93db3
arty: Add configuration of I2S pins
2020-07-07 15:25:10 +02:00
40fbbbbebc
platforms/orangecrab: add sdcard pins on r0_2.
2020-07-06 17:48:48 +02:00
49973990f3
Merge pull request #85 from oskirby/logicbone
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Add Logicbone ECP5 board
2020-06-29 16:24:15 +02:00
76a32ba8ec
Add Logicbone ECP5 board
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The Logicbone is an Open Source development board for the Lattice ECP5
being developed at https://github.com/oskirby/logicbone
2020-06-27 03:32:47 -07:00
782c856619
platforms/genesys2: add usb_fifo.
2020-06-23 18:02:53 +02:00
936ba5b279
platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG).
2020-06-23 11:55:50 +02:00
55ed9fbf02
platforms/kcu105: add sdcard/spisdcard.
2020-06-23 11:44:40 +02:00
eee00ebd0a
platforms/genesys2: add sdcard/spisdcard.
2020-06-23 11:44:26 +02:00
6568c8a3ae
platforms/netv2: add spisdcard.
2020-06-23 11:44:10 +02:00
7de7c4be5c
platforms/kc705: rename mmc to sdcard and make it similar to other boards.
2020-06-23 10:56:31 +02:00
0ecb8609b3
platform/arty: also update spisdcard.
2020-06-16 20:15:12 +02:00
7a8b0b743d
platforms/pano_logic_g2: -x.
2020-06-16 19:53:46 +02:00
f70655d1ac
Change sdcard Pmod from JB to JD
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Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2020-06-15 12:01:46 +02:00
04f6d4463a
versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt.
2020-06-13 11:17:05 +02:00
90092164c8
Add device option for ECP5 Versa board
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Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
2020-06-12 18:39:43 -05:00
9b45ec0f35
de10lite: simplify vga terminal.
2020-06-11 19:59:32 +02:00
85cac7abc0
de10nano/Mister: review/simplify.
2020-06-11 19:54:55 +02:00
c94cbae0c0
orangecrab: add user_led (RGB leds), DFUProg and --load support.
2020-06-11 19:21:40 +02:00
9aea2272eb
Merge pull request #80 from rob-ng15/master
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Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-11 18:16:18 +02:00
ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e
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Add Colorlight 5A-75E V7.1 board
2020-06-10 23:09:26 +02:00
b312c65eb9
Merge pull request #81 from Disasm/fix-5a-75b
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Update J4 pin 5 on Colorlight 5A-75B V7.0
2020-06-10 23:07:33 +02:00
b6df166f5a
platforms/arty: add spisdcard to _sdcard_pmod_io.
2020-06-10 17:38:16 +02:00
00c8e40d02
platforms/ulx3s: add sdcard pins.
2020-06-10 17:37:50 +02:00
1acdb962a5
Add 5A-75E V7.1 board
2020-06-10 03:07:20 +03:00
939f05fea4
Update J4 pin 5 on Colorlight 5A-75B V7.0
2020-06-10 02:49:18 +03:00
e52d6aca5f
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
2020-06-08 11:05:36 +01:00
0b11aba8a1
platforms/nexys_video: add spisdcard pins.
2020-05-29 19:37:04 +02:00
33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read
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ZCU104: add I2C
2020-05-27 14:56:31 +02:00
e5578a1ae8
zcu104/platform: change I2C number to 0
2020-05-27 14:31:22 +02:00
ac1f1cd6a7
zcu104: add I2C
2020-05-27 12:47:43 +02:00
2f3817cba9
pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst.
2020-05-27 10:13:12 +02:00
f19bc36813
pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer.
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Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
2020-05-27 08:58:40 +02:00
0648c04158
Updated comment, added link to clocking documentation.
2020-05-25 14:48:24 -07:00
1ab46562bd
Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200)
2020-05-25 10:11:03 -07:00
9b572ece0e
forest_kitten_33: add minimal target and use es1.
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Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X
2020-05-25 12:26:52 +02:00
0d549a8c89
platforms: add forest_kitten_33 initial platform suppport.
2020-05-24 11:22:02 +02:00
12b54a7a7f
platforms/alveo_u250: add clk300 clock constraints.
2020-05-24 11:18:30 +02:00
46f78b5002
nexys_video: add usb_fifo pins.
2020-05-22 14:28:55 +02:00
445338e2e7
platforms/nexys_video: add specific openocd cfg (use channel 1).
2020-05-22 14:12:45 +02:00
76551dec4c
platforms/nexys_video: add sdcard pins, move clk/rst to top.
2020-05-20 13:05:18 +02:00
83457b8791
platforms/arty: add _sdcard_pmod_io.
2020-05-20 12:09:43 +02:00
587caf7584
paltforms/marblemini: add break_off_pmod.
2020-05-19 15:42:53 +02:00
c2cd863658
platforms/ecp5_evn: rename spiflash1x to spiflash, rewrite hardware/configuration description and remove make_spiflash.
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The Platform file should not contain import code related to cores, this has to be done in the target.
2020-05-19 15:29:25 +02:00
3f0f12011b
Merge pull request #70 from ilya-epifanov/ecp5-evn-spi1x-and-flash-params
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ECP5-EVN SpiFlash parameters
2020-05-19 15:16:25 +02:00
b9ee3a797a
alveo_u250: re-organize the auto-generated IOs, add build/load parameters.
2020-05-16 11:47:14 +02:00
6757c4e298
Merge pull request #71 from daveshah1/alveo_u250
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[WIP] Add Alveo U250 platform and target
2020-05-13 09:10:22 +02:00
4faa91c7f2
platforms/marblemini: review/cleanup.
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- add copyrights.
- add link to documentation.
- reindent code.
- rename some IOs (for consistency with the others platforms).
- add pullup on clk20_vcxo_en.
- set clk20_vcxo as default clock.
- remove ununnecessary eth constraints. (we are using IO primitives).
- move PMODS to connectors (for consistency with others platforms).
2020-05-09 10:16:42 +02:00
4ffdcb5ea9
Merge pull request #75 from jersey99/marblemini
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Marblemini [https://github.com/berkeleylab/marble-mini/ ]
2020-05-09 09:39:40 +02:00
e4ccfcfad1
platforms/marblemini.py: Cleanup. Add openocd for programming marblemini
2020-05-08 17:20:14 -07:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
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Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
a7d6de78ae
Merge branch 'master' into marblemini
2020-05-07 12:19:47 -07:00
99c04358bf
platforms/pano_logic_g2: simplify/cleanup.
2020-05-07 16:35:34 +02:00
6b5492a707
pano_logic_g2: add copyrights.
2020-05-07 15:24:03 +02:00
6ddd859309
add pano_logic_g2 from litex-buildenv.
2020-05-07 15:22:22 +02:00
d34c3baf15
prog: use different openocd config files for FT232/FT2232.
2020-05-06 16:14:51 +02:00
e500d90bcc
platforms/ecpix5: set pullups on rx_data to advertise as RGMII mode.
2020-05-06 16:00:46 +02:00
59e8c2cd30
acorn_cle_215: add .bin generation and --flash argument, working on hardware :).
2020-05-06 12:27:07 +02:00
a049fa6856
add Acorn CLE 215+ platform/target.
2020-05-06 07:53:55 +02:00
b58b9b9e6a
platforms: fix CI.
2020-05-05 16:01:43 +02:00
19eb5708de
platforms: make sure all traditional platforms have a create_programmer method.
2020-05-05 13:34:57 +02:00
Florent Kermarrec
David Shah
DerFetzer
Piense
connorwk
Pawel Sagan
Pepijn de Vos
rob-ng15
Vamsi K Vytla
Greg Davill
Owen Kirby
Kamil Rakoczy
Raptor Engineering Development Team
Vadim Kaushan
Jędrzej Boczar
Skip Hansen
Vamsi K Vytla