Florent Kermarrec
|
028d4a78aa
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targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
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2020-01-13 15:20:37 +01:00 |
|
Florent Kermarrec
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15f3457aea
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platforms/de0nano/serial: add gpio names in comment
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2020-01-10 18:53:52 +01:00 |
|
Florent Kermarrec
|
7afe3dc674
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platforms/targets: sync with litex
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2020-01-09 21:10:59 +01:00 |
|
Florent Kermarrec
|
4192b20f09
|
targets: cleanup Altera CRGs
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2020-01-09 19:46:39 +01:00 |
Gabriel Somlo
|
d08dfdb808
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platforms/nexys4ddr: add sdcard pins (sync w. litex commit #e99740e8)
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2020-01-09 09:25:19 -05:00 |
|
Florent Kermarrec
|
babbc676eb
|
targets: cleanup ECP5 CRGs
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2020-01-09 14:24:18 +01:00 |
|
Florent Kermarrec
|
d91458c3e6
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targets/versa_ecp5: fix compilation with diamond
|
2019-12-06 16:16:19 +01:00 |
|
Florent Kermarrec
|
30ea463b41
|
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
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2019-12-06 16:01:59 +01:00 |
|
Florent Kermarrec
|
1b1370d086
|
official/targets: uniformize, improve presentation
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2019-12-03 09:07:09 +01:00 |
|
Florent Kermarrec
|
1ae26dd499
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targets: use type="io" instead of io_region=True
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2019-10-30 16:35:32 +01:00 |
|
Gabriel Somlo
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8878c0a84a
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versa_ecp5, trellisboard: add trellis toolchain specific arguments
Sync up with Litex commit #49372852d.
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2019-10-29 12:32:41 -04:00 |
|
Gabriel Somlo
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5f80633154
|
targets: increase integrated ROM size if EthernetSoC used
Sync up with litex commit #201218b2c.
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2019-10-29 12:32:41 -04:00 |
|
Gabriel Somlo
|
c83e10d9f3
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official/platforms/versa_ecp5: add serdes refclk/sma
Sync up with litex commit #ae9c25b74.
|
2019-10-29 12:32:41 -04:00 |
|
Florent Kermarrec
|
785909ac5f
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targets: switch from shadow_base to io_regions
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2019-10-09 11:09:59 +02:00 |
|
Florent Kermarrec
|
48cd1208df
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targets: sync with litex targets
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2019-09-25 14:09:25 +02:00 |
|
Florent Kermarrec
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b4eefa6c33
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import: allow importing directly from litex_boards.platforms or litex_boards.targets
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2019-09-03 15:30:20 +02:00 |
|
Florent Kermarrec
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e704014b36
|
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
|
2019-09-01 11:43:21 +02:00 |
|
Florent Kermarrec
|
1131af05af
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nexys_video: generate clk100
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2019-08-27 14:05:07 +02:00 |
|
Florent Kermarrec
|
ac58d57a83
|
targets: import platforms from litex_boards.platforms
|
2019-08-26 09:09:40 +02:00 |
|
Florent Kermarrec
|
b84308cb58
|
list all platforms/targets in platforms.py, targets.py to ease import
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2019-08-26 09:07:07 +02:00 |
|
Florent Kermarrec
|
9f3ed82097
|
keep up to date with LiteX
- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
|
2019-08-07 08:47:08 +02:00 |
|
Florent Kermarrec
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82d73b8359
|
Merge branch 'master' of http://github.com/litex-hub/litex-boards
|
2019-07-12 19:19:31 +02:00 |
|
Florent Kermarrec
|
debafd7c17
|
official/partner: update
|
2019-07-12 19:19:01 +02:00 |
|
Florent Kermarrec
|
325b6399a2
|
add test/test_targets (only test platforms with simple target for now)
|
2019-06-24 12:38:58 +02:00 |
|
Florent Kermarrec
|
aeddb93729
|
add copyright header to all files, udpate.
|
2019-06-24 12:13:54 +02:00 |
|
Florent Kermarrec
|
44d01edab9
|
dispatch platforms/targets by level of support
|
2019-06-10 18:59:49 +02:00 |
|
Florent Kermarrec
|
4213c75e48
|
init repo with litex official boards
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2019-06-10 17:11:36 +02:00 |