Florent Kermarrec
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908539d49f
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targets/nexys4ddr: fix typo
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2020-01-17 13:15:22 +01:00 |
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Florent Kermarrec
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bb99a8dd0c
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targets/kcu105: remove main_ram_size_limit
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2020-01-17 12:09:53 +01:00 |
|
Florent Kermarrec
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fd1e655700
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targets: cleanup EthernetSoC
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2020-01-16 10:28:09 +01:00 |
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Florent Kermarrec
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028d4a78aa
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targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
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2020-01-13 15:20:37 +01:00 |
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Florent Kermarrec
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7afe3dc674
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platforms/targets: sync with litex
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2020-01-09 21:10:59 +01:00 |
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Florent Kermarrec
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4192b20f09
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targets: cleanup Altera CRGs
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2020-01-09 19:46:39 +01:00 |
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Florent Kermarrec
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babbc676eb
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targets: cleanup ECP5 CRGs
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2020-01-09 14:24:18 +01:00 |
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Florent Kermarrec
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d91458c3e6
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targets/versa_ecp5: fix compilation with diamond
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2019-12-06 16:16:19 +01:00 |
|
Florent Kermarrec
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30ea463b41
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targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
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2019-12-06 16:01:59 +01:00 |
|
Florent Kermarrec
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1b1370d086
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official/targets: uniformize, improve presentation
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2019-12-03 09:07:09 +01:00 |
|
Florent Kermarrec
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1ae26dd499
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targets: use type="io" instead of io_region=True
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2019-10-30 16:35:32 +01:00 |
Gabriel Somlo
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8878c0a84a
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versa_ecp5, trellisboard: add trellis toolchain specific arguments
Sync up with Litex commit #49372852d.
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2019-10-29 12:32:41 -04:00 |
|
Gabriel Somlo
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5f80633154
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targets: increase integrated ROM size if EthernetSoC used
Sync up with litex commit #201218b2c.
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2019-10-29 12:32:41 -04:00 |
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Florent Kermarrec
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785909ac5f
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targets: switch from shadow_base to io_regions
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2019-10-09 11:09:59 +02:00 |
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Florent Kermarrec
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48cd1208df
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targets: sync with litex targets
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2019-09-25 14:09:25 +02:00 |
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Florent Kermarrec
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b4eefa6c33
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import: allow importing directly from litex_boards.platforms or litex_boards.targets
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2019-09-03 15:30:20 +02:00 |
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Florent Kermarrec
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e704014b36
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targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
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2019-09-01 11:43:21 +02:00 |
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Florent Kermarrec
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1131af05af
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nexys_video: generate clk100
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2019-08-27 14:05:07 +02:00 |
|
Florent Kermarrec
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ac58d57a83
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targets: import platforms from litex_boards.platforms
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2019-08-26 09:09:40 +02:00 |
|
Florent Kermarrec
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b84308cb58
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list all platforms/targets in platforms.py, targets.py to ease import
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2019-08-26 09:07:07 +02:00 |
|
Florent Kermarrec
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9f3ed82097
|
keep up to date with LiteX
- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
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2019-08-07 08:47:08 +02:00 |
|
Florent Kermarrec
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82d73b8359
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Merge branch 'master' of http://github.com/litex-hub/litex-boards
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2019-07-12 19:19:31 +02:00 |
|
Florent Kermarrec
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debafd7c17
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official/partner: update
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2019-07-12 19:19:01 +02:00 |
|
Florent Kermarrec
|
325b6399a2
|
add test/test_targets (only test platforms with simple target for now)
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2019-06-24 12:38:58 +02:00 |
|
Florent Kermarrec
|
aeddb93729
|
add copyright header to all files, udpate.
|
2019-06-24 12:13:54 +02:00 |
|
Florent Kermarrec
|
44d01edab9
|
dispatch platforms/targets by level of support
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2019-06-10 18:59:49 +02:00 |
|
Florent Kermarrec
|
4213c75e48
|
init repo with litex official boards
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2019-06-10 17:11:36 +02:00 |