inc
fec82c59e2
remove konfekt ethernet option
2022-12-30 17:36:52 +01:00
inc
f0dc9a6874
initial support for machdyne konfekt and noir
2022-12-30 17:00:35 +01:00
stone3311
6cfb56bb07
terasic_deca: add SPI SD card support
2022-12-28 02:13:06 +01:00
jiv4ik
57845d1ca4
Correct pinout and IOStandard
...
Correct connector pinout
Correct pinout for ETH
LED IOStandard set to LVCMOS33
BTN[0] IOStandard set to LVCMOS33
Changes are made based on Tang_primer_20K_3690 and Tang_Primer_20K-Dock_3709 schemes.
2022-12-22 18:30:36 +03:00
Gwenhael Goavec-Merou
4e06e5ff9c
targets/xilinx_zybo_z7: adding missing variant parameter to the platform
2022-12-14 07:47:09 +01:00
Gwenhael Goavec-Merou
a92fdffb35
platforms/digilent_zybo_z7: reorder _io_x & _connectors_x, init cleanup
2022-12-12 22:17:39 +01:00
JoyBed
d28894a4b3
Reintroduce original Zybo + HDMI addition ( #461 )
...
* Reintroduce original Zybo support
* Reintroduce original zybo, add HDMI + fixes for Z7
2022-12-12 22:05:47 +01:00
Florent Kermarrec
12db52471d
targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash).
2022-12-08 08:37:13 +01:00
enjoy-digital
c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config
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Arty z7 tcl config
2022-12-08 08:31:22 +01:00
enjoy-digital
71f1e1976b
Merge pull request #459 from tcal-x/icebitsy-ledchaser
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Add LedChaser to iCEBreaker-bitsy.
2022-12-06 09:05:37 +01:00
Guilherme Salustiano
25c40ddda7
add gpio to board
2022-12-05 21:38:56 -03:00
Tim Callahan
6e205be83b
Add LedChaser to iCEBreaker-bitsy.
...
Signed-off-by: Tim Callahan <tcal@google.com>
2022-12-04 17:58:20 -08:00
Gwenhael Goavec-Merou
a889321535
targets/digilent_arty_z7: adding note to load gateware and bios
2022-12-03 16:54:52 +01:00
Gwenhael Goavec-Merou
e71e3ab3ec
platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration
2022-12-03 16:54:39 +01:00
Guilherme Salustiano
d0d90e9eef
Merge branch 'litex-hub:master' into master
2022-11-29 15:25:41 -03:00
Gwenhael Goavec-Merou
b030630237
Merge pull request #453 from cklarhorst/zybo
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Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
2022-11-25 21:48:43 +01:00
mkuhn99
53b6bf035a
fixed parser
2022-11-24 16:03:12 +01:00
mkuhn99
926ed21f0b
fixed review remarks; added zynq7000 as a submodule for using the ps as a slave
2022-11-23 17:20:25 +01:00
Guilherme Salustiano
570ea11744
fix(plataform.basys_3): V_sync is pin R19
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Based in https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#LL129C34-L129C37
2022-11-23 09:16:50 -03:00
mkuhn99
c489347a51
fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC
2022-11-18 11:19:57 +01:00
mkuhn99
6f7716adbb
added config for ps7; introduced different variants for the zybo-board; fixed pins
2022-11-18 11:15:54 +01:00
Icenowy Zheng
892bf3546d
isx_im1283: connect CRG reset to PLL
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This fixes soft reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-16 15:12:18 +08:00
Icenowy Zheng
e27d8c958e
isx_im1283: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-15 21:07:10 +08:00
Florent Kermarrec
ae47172d2a
targets/decklink_mini_4k: Update clock constraints.
2022-11-14 10:21:42 +01:00
Florent Kermarrec
6e10df234f
platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau).
2022-11-14 10:21:37 +01:00
Icenowy Zheng
e9d7013d70
sitlinv_stlv7325: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:28:04 +08:00
Icenowy Zheng
c2c59f5e8c
sitlinv_stlv7325: allow to set local/remote ip
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Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:58 +08:00
Icenowy Zheng
3d8106f84d
stlv7325: fix Ethernet IO voltages
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The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.
Fix this in the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
Icenowy Zheng
27c3afb8fb
sitlinv_stlv7325: allow dynamic Ethernet IP
...
Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.
Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
Icenowy Zheng
4ba5793822
sitlinv_stlv7325: remove unexistent COL/CRS pins
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The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.
Remove these pins from the platform definition.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
Icenowy Zheng
1c07fa94ca
sitlinv_stlv7325: fix ident string vendor name
...
As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.
Fix this too.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
Florent Kermarrec
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
Florent Kermarrec
a8c92cd86f
targets/simple: Switch back to old version for now.
2022-11-08 11:55:06 +01:00
Florent Kermarrec
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
Florent Kermarrec
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
Florent Kermarrec
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
Florent Kermarrec
f1e24046fd
xilinx_alveo_u250: Fix.
2022-11-06 22:17:28 +01:00
enjoy-digital
6edfb2ca7a
Merge pull request #448 from trabucayre/fix_alinx_axu2cga_platform
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platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 22:11:25 +01:00
Florent Kermarrec
9a2028a9ba
targets: Remove useless argparse imports.
2022-11-06 22:09:21 +01:00
Florent Kermarrec
30723b1bb0
targets: Update targets that were still using argparse.ArgumentParser.
2022-11-06 22:07:17 +01:00
Gwenhael Goavec-Merou
24cd983b8c
platforms/alinx_axu2cga: adding missing psu_config at platform level
2022-11-06 21:52:00 +01:00
Florent Kermarrec
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
Gwenhael Goavec-Merou
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
Icenowy Zheng
d7184fb043
stlv7325, a_e115fb: use the proper vendor name Sitlinv
...
The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.
Use this vendor name instead of where it's bought.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-30 10:51:13 +08:00
enjoy-digital
4dc8f7223c
Merge pull request #443 from trabucayre/arty_z7_bios
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targets/digilent_arty_z7: adding software support
2022-10-28 10:42:35 +02:00
Florent Kermarrec
3e809c3a1e
targets: Fix some LiteXModule imports.
2022-10-28 10:35:57 +02:00
Florent Kermarrec
ab3ed624cc
fpgawars_alhambra2: +x.
2022-10-28 10:31:49 +02:00
Gwenhael Goavec-Merou
5f1b80fac4
targets/digilent_arty_z7: adding software support
2022-10-27 21:47:32 +02:00
Florent Kermarrec
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
enjoy-digital
6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name
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platforms/nexys4*: Update part name
2022-10-27 12:11:07 +02:00
Chema
f9d3a39001
chore fix target, args processing
2022-10-26 20:45:53 +02:00
Chema
189ee3de39
fix target
2022-10-26 20:36:18 +02:00
Chema
54af30a4be
fix: arg cpu-variant
2022-10-26 20:23:14 +02:00
Chema
32be05cfb1
chore default CPU variant
2022-10-25 21:14:25 +02:00
Chema
125569b2cb
add FPGAWars Alhambra II
2022-10-25 21:12:02 +02:00
Florent Kermarrec
bd2f1c2553
targets/isx_im1283: Fix CI.
2022-10-22 16:23:50 +02:00
enjoy-digital
8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region
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targets/redpitaya: fix csr & reset region
2022-10-22 16:00:22 +02:00
enjoy-digital
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283
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Add ISX iM1283 board
2022-10-22 15:56:43 +02:00
Shawn Anastasio
d4b2461b5a
platforms/nexys4*: Update part name
...
Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
2022-10-21 14:15:27 -05:00
Florent Kermarrec
5a8d846a86
targets: Remove add_csr calls (no longer required).
2022-10-21 08:42:24 +02:00
Florent Kermarrec
377cda05a3
ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity.
...
Will need to be investigated more.
2022-10-20 18:21:52 +02:00
Gwenhael Goavec-Merou
4a5d5318d7
targets/redpitaya: fix csr & reset region
2022-10-20 16:35:57 +02:00
Icenowy Zheng
745ebbbfa1
Add ISX iM1283 board
...
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.
This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-14 22:50:43 +08:00
enjoy-digital
cb65099399
Merge pull request #435 from trabucayre/fix_artyz7_build
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targets/digilent_arty_z7: add flash region
2022-10-14 15:49:52 +02:00
Florent Kermarrec
23c6acd013
platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks.
...
Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.
Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+ table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
2022-10-14 10:22:54 +02:00
Gwenhael Goavec-Merou
e44e63f65d
targets/digilent_arty_z7: add flash region
2022-10-13 19:48:41 +02:00
Florent Kermarrec
3b339ba9a3
platforms/xilinx_kc705: Fix flash proxy name.
2022-10-13 08:48:33 +02:00
Florent Kermarrec
99888c52ce
xilinx_kc705/i2c: Add pullups.
2022-10-11 17:26:06 +02:00
Franck Jullien
3ec18c3583
Add qmtech Cyclone IV Starter Kit
2022-10-09 16:34:44 +02:00
Florent Kermarrec
e6762e228c
targets/mnt_rkx7: Make USB-Host optional and disable by default (for CI).
2022-10-04 09:45:51 +02:00
Florent Kermarrec
d0dd009329
targets/mnt_rkx7: Integrate specific eDP video timings in target (Avoid LiteX patch).
2022-10-04 09:29:59 +02:00
Lukas F. Hartmann
c38b8b1d8c
MNT RKX7: update platform and target for D-2 release
2022-10-03 20:09:48 +02:00
Vadzim Dambrouski
cf416d0d66
stlv7325: Adjust DDR3 pins to match reference design
2022-10-01 11:15:47 +02:00
Gwenhael Goavec-Merou
85ba931a3d
targets/litex_acorn_baseboard: fix pn_swap
2022-09-28 21:17:16 +02:00
Vadzim Dambrouski
57eb907210
aliexpress_stlv7325: Fix missing parameter for PULLUP attribute
2022-09-25 23:13:44 +02:00
Florent Kermarrec
8c3a5c0608
sipeed_tang_nano_9k: Fix HDMI IOs constraints.
2022-09-23 11:18:30 +02:00
Florent Kermarrec
9cd1c1cbd5
targets/digilent_arty: Switch with_buttons to False by default (To fix #426 ).
2022-09-23 10:07:17 +02:00
slagernate
9dbee62eac
add option to use ecpprog for crosslink-nx eval board
2022-09-15 12:27:08 -07:00
Florent Kermarrec
3cef11e04d
platforms/newae_cw305: Add sma_clk_in/out, buttons, switches and expansion header connector.
2022-09-13 14:26:52 +02:00
Florent Kermarrec
f1899954e9
Add initial NewAE CW305 board support.
2022-09-13 12:38:30 +02:00
Adam Zeloof
25c28d2c03
fixed issue with default programmer option
2022-09-10 18:16:04 +01:00
Adam Zeloof
6768be7f66
changed use example comment
2022-09-10 17:56:02 +01:00
Adam Zeloof
e8504191e3
cleanup
2022-09-10 17:54:43 +01:00
Adam Zeloof
6d0a4c788e
Added DFU support to Butterstick
2022-09-10 17:45:57 +01:00
Florent Kermarrec
756e4f73fc
sipeed_tang_primer_20k: Cleanup CRG.
2022-09-08 17:27:41 +02:00
Florent Kermarrec
fadc5619f1
sipeed_tang_primer_20k/ddr3: Add litescope debug.
2022-09-07 17:46:46 +02:00
Florent Kermarrec
6c7157f799
sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status.
2022-09-07 17:07:07 +02:00
Florent Kermarrec
d39d87b701
sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules.
2022-09-07 12:06:22 +02:00
Icenowy Zheng
1663ded641
sipeed_tang_primer_20k: Add initial DDR3 integration (WIP).
2022-09-07 11:53:24 +02:00
Florent Kermarrec
c9b8579ea3
sipeed_tang_primer_20k: Drive hdmi hdp to 1.
2022-09-07 11:22:02 +02:00
Florent Kermarrec
abd20f560b
sipeed_tang_primer: Minor cleanups (Rename standard dock to standard, reduce margin on hdmi5x).
2022-09-07 10:56:17 +02:00
Gwenhael Goavec-Merou
1d92443604
targets/sipeed_tang_nano_9k: replace VideoHDMIPHY by VideoGowinHDMIPHY
2022-09-06 20:22:32 +02:00
Gwenhael Goavec-Merou
4d72c75f49
platforms/sipeed_tang_primer_20k: use replace _connectors.extend by add_connector
2022-09-06 20:19:37 +02:00
Gwenhael Goavec-Merou
0f242629ab
targets/sipeed_tang_nano_4k: replacing VideoHDMIPHY by VideoGowinHDMIPHY and adding with-video-terminal arg
2022-09-06 19:08:01 +02:00
Gwenhael Goavec-Merou
ce5977bc1a
targets/sipeed_tang_primer_20k: fix CLKDIV (disable reset and calibration)
2022-08-31 13:32:23 +02:00
Florent Kermarrec
74d4a72494
radiona/ulx3s: Rename user_button to user_btn (consistency with other boards) and fix ident.
2022-08-26 22:25:54 +02:00
enjoy-digital
693cce73bd
Merge pull request #417 from Igor542/master
...
radiona_ulx3s: add buttons
2022-08-26 22:24:05 +02:00
Gwenhael Goavec-Merou
0c14bbf0dc
sipeed_tang_primer_20k: adding dock lite support
2022-08-26 08:43:57 +02:00
Igor Safonov
9ed3b7baae
radiona_ulx3s: add buttons
2022-08-25 22:19:48 -07:00
Florent Kermarrec
94d079f469
sipeed_tang_nano_4k: Fix tab/space.
2022-08-24 16:07:18 +02:00