c5d1a252c5
targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM.
2024-08-28 15:53:53 +02:00
4002b8167c
Merge pull request #602 from trabucayre/fix_tangPrimer20k_iostandard
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platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-19 17:14:25 +02:00
52fc033bf5
Merge pull request #599 from trabucayre/sipeed_tang_gw5A_SDRAM
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Sipeed tang gw5 a sdram
2024-08-19 17:12:48 +02:00
a9504502fe
Merge pull request #598 from malled2002/fix-enclustra-kx2
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enclustra mercury kx2+: fix pinnumber on connector C
2024-08-19 17:11:37 +02:00
a5ee3c807a
platforms/sipeed_tang_primer_20k.py: fix IOStandard values
2024-08-14 09:16:39 +02:00
b1a6da84b3
sipeed_tang_primer_25k: add SDRAM support (j3 connector), allows user to select between mister and sipeed SDRAM module
2024-08-04 12:14:56 +02:00
2fa838b79d
sipeed_tang_mega_138k_pro: added SDRAM sipeed variant, allows user to select between mister and sipeed SDRAM module, fix sipeed SDRAM memory module
2024-08-04 12:13:47 +02:00
241dfb6780
fix pinnumber on connector C
2024-08-01 19:14:49 +02:00
81209b9fd1
platforms/enclustra_mercury_xu8_pe3: Revert to VivadoProgrammer since OpenFPGALoader is not albe to load bitstream correctly if FPGA is not already configured.
2024-07-22 15:28:25 +02:00
938bf8b3a6
targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR
2024-07-22 15:18:27 +02:00
ab732011b3
plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints
2024-07-22 14:49:03 +02:00
5d4ebeb09c
targets: Add initial Enclustra Mercury+ XU8/PE3 target with DRAM and PCIe.
2024-07-22 11:40:19 +02:00
0394b626fa
platforms/enclustrat_mercury_xu8_pe3: Switch to OpenFPGALoader for loading FPGA.
2024-07-22 11:39:17 +02:00
8f8e0bd228
targets/enclustra: Add Enclustra to identifier.
2024-07-22 11:38:22 +02:00
f844d06da2
targets/litex_acorn_baseboard_mini: Add detect_ftdi_chip method since newer batch of baseboard is mounted with FTDI ft4232 chips.
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FT2232 and FT4232 chips are footprint compatible but still need to be handled differently from software.
2024-07-19 15:43:25 +02:00
6d3c87a6f7
platforms/lattice_certuspro_nx_versa: Fix default_clk.
2024-07-17 15:14:53 +02:00
fff2e6bd3f
platform: Add Lattice CertusPro-NX Versa initial support.
2024-07-17 14:53:12 +02:00
88ab3eca6f
targets: Map SPRAM to SRAM when use as SRAM.
2024-07-17 11:01:34 +02:00
524387b45d
sqrl_xcu1525: Fix typo.
2024-07-11 12:54:38 +02:00
e94e84eb16
sqrl_xcu1525: Add more QSFP IOs.
2024-07-10 18:20:01 +02:00
c7b436a202
sqrl_xcu1525: Add QSFP-0/1 ref clks and rearrange a bit naming.
2024-07-10 17:04:48 +02:00
00df115e86
sqrl_xcu1525: Add QSFP-0/1 IOs.
2024-07-10 16:44:12 +02:00
0ed9e3ac85
Merge pull request #596 from gaoyichuan/vcu118-fmc
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platforms/xilinx_vcu118: add fmc and pmod connector pinouts
2024-07-10 09:17:41 +02:00
5870b078f8
platforms/xilinx_vcu118: add fmc and pmod connector pinouts
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VCU118 board has one FMC HPC, one FMC+ HSPC and two PMOD connectors,
Vivado board files does not contain pinouts for these, so pinouts are
taken from VCU118 Evaluation Board User Guide (UG1224).
Signed-off-by: Yichuan Gao <gaoyichuan000@gmail.com>
2024-07-06 00:16:53 +08:00
15c6f89b1a
#570 : Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007 .
2024-07-05 10:26:28 +02:00
2e120bf8a4
Merge pull request #570 from disdi/master
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Add support for CTUCAN for Arty & Genesys2 board
2024-07-05 09:21:09 +02:00
ac427feb0a
targets/lattice_certuspro_nx_vvml,lattice_certuspro_nx_evn: switch sys_clk to NXPLL
2024-07-03 12:36:28 +02:00
9898672744
siglent_sdr1104xe: Update IP/MAC addresses.
2024-07-02 17:09:23 +02:00
7a157d787b
lattice_certus_prox_nx: Add missing OpenFPGAALoader import.
2024-07-01 15:58:31 +02:00
1c06988d80
platforms,targets/lattice_certuspro_nx_evn,lattice_certuspro_nx_vvml: set sysconfig SPI_MASTER mode by default at platform level
2024-07-01 11:07:25 +02:00
40204ac815
Merge pull request #595 from trabucayre/lattice_certusnxpro
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Lattice certusnxpro
2024-06-28 13:26:47 +02:00
5813df9b44
Merge pull request #591 from VOGL-electronic/efinix_trion_t20_pulse_reset
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targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
2024-06-28 13:24:29 +02:00
8579af5710
lattice_certuspro_nx_vvml: new board support
2024-06-28 12:47:57 +02:00
f27bbc9645
lattice_certuspro_nx_evn: new board support
2024-06-28 12:47:16 +02:00
bd58227c86
platforms/sqrl_acorn/_litex_acorn_baseboard_mini_io: Add SFP-I2C and Debug IOs.
2024-06-27 14:55:15 +02:00
4f8540d53e
targets/litex_acorn_baseboard_mini: Switch to _litex_acorn_baseboard_mini_io.
2024-06-27 14:23:43 +02:00
91e787b5c3
platforms/sqrl_acorn: Add _litex_acorn_baseboard_mini_io for LiteX Acorn Baseboard Mini specific IOs.
2024-06-27 14:23:17 +02:00
c205bb756b
targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
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to do a reset on the trion t20 a pulse is needed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-06-24 09:14:55 +02:00
75ef26b8e5
platforms/machdyne_mozart_mx1.py: adding default_clk_name, default_clk_period (fix CI failure)
2024-06-22 22:43:06 +02:00
f8d41e880d
Merge pull request #593 from machdyne/master
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machdyne: fix typos; add vanille and lakritz
2024-06-22 21:43:02 +02:00
cb43cdf6f9
targets/machdyne_vanille: set uart_name to stub
2024-06-22 12:13:30 +02:00
a1df389c7e
machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
2024-06-22 11:26:43 +02:00
5d62eec8a8
README.md: add vanille and lakritz
2024-06-22 09:32:15 +02:00
34e85c5cf6
machdyne: fix typos; add vanille and lakritz
2024-06-22 09:26:42 +02:00
95f5e030e5
Merge pull request #590 from trabucayre/zynq_csr_master_bus
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ZynqXXX boards: remove CSR definition and GP0 connection to CPU
2024-06-19 08:48:33 +02:00
dad6b2b9b6
efinix_trion_t20_bga256_dev_kit: Cleanup/Review platform/target.
2024-06-19 08:23:54 +02:00
8eaa4d637e
Merge pull request #589 from VOGL-electronic/sdram_efinix_trion_t20
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efinix_trion_t20: add sdram
2024-06-19 08:18:19 +02:00
70fb3de96c
targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
2024-06-19 07:59:24 +02:00
efd6c8b0aa
targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU
2024-06-19 07:54:50 +02:00
07881259a5
litex_acorn_baseboard_mini: Assert cleanups.
2024-06-18 17:41:01 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Malte
Gwenhael Goavec-Merou
Yichuan Gao
Fin Maaß
inc