c3d8c7462d
test/test_targets: update
2020-02-03 09:44:22 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
7a24406b2e
targets: fomu: fix compatibility for when a cpu is added
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Things weren't quite right for adding a CPU. This fixes that by
correcting the placer arguments, memory map, and USB type.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-03 08:58:54 +08:00
0627f55dca
de10nano: cleanup a bit, rename SDRAMSoC to MiSTerSDRAMSoC and argument to --with-mister-sdram to make it clear that it's using the MiSTer SDRAM extension board.
2020-01-31 09:29:02 +01:00
cf9a9ff91b
de10nano: update copyrights, remove trailing whitespaces
2020-01-31 09:13:36 +01:00
4f85d50ff5
Merge pull request #39 from sajattack/de10nano
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Add de10 nano board
2020-01-31 09:08:19 +01:00
36e1f1fe75
rename sw to user_sw
2020-01-30 05:01:46 -08:00
1631b071c3
finish up sdram, passes memtest
2020-01-30 03:41:44 -08:00
5091a1b40a
WIP sdram module option
2020-01-29 13:59:57 -08:00
3a6a9258ce
add de10 nano board
...
add iostandard to hdmi
2020-01-29 00:21:51 -08:00
2ec6bc0bdc
colorlight_5a_75b: add disclaimer
2020-01-23 14:13:13 +01:00
55c0b781e4
colorlight_5a_75b: revert rx_delay to 2ns, improve comment (thanks @tnt)
2020-01-23 13:16:36 +01:00
4fb89fc9c5
colorlight_5a_75b: set RGMII tx/rx_delay to 0ns in the FPGA (added by PCB/PHY)
2020-01-23 09:39:48 +01:00
dcc65b347d
targets/colorlight_5a_75b: switch to SoCCore, CPU and Etherbone working :)
...
Tested with:
./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv
Load with following script:
#!/usr/bin/env python3
# Load ---------------------------------------------------------------------------------------------
def load():
import os
f = open("openocd.cfg", "w")
f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
f.close()
os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
exit()
if __name__ == "__main__":
load()
Then start lxserver:
lxserver --udp
And run following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
while True:
if wb.regs.uart_xover_rxempty.read() == 0:
print(chr(wb.regs.uart_xover_rxtx.read()), end="")
sys.stdout.flush()
# # #
wb.close()
2020-01-22 15:57:52 +01:00
c07e4a6b3a
colorlight_5a_75b: fix rst_n
2020-01-22 14:57:48 +01:00
8da8ed7a0e
colorlight_5a_75b/v7.0: update eth_clocks/rx pinout, remove FIXME
2020-01-22 14:56:17 +01:00
bb805999cb
platforms/colorlight_5a_75b: fix 6.1 used_led_n/user_btn_n thanks @smunaut
2020-01-22 12:43:37 +01:00
43badd162e
colorlight_5a_75b/v6.1: add led/btn and remove FIXME on sdram now that clarified
2020-01-22 11:05:08 +01:00
1d9e349093
partner: add colorlight_5a_75b initial support
2020-01-22 09:51:00 +01:00
07067301d5
targets/linsn_rv901t: cleanup arguments
2020-01-22 09:04:28 +01:00
8113b491db
aller/nereid/tagus: update litepcie
2020-01-21 21:26:23 +01:00
684c1640bb
add Linsn RV901T support
2020-01-18 21:40:04 +01:00
0e4569a48a
platforms/camlink_4k: remove #!/usr/bin/env python3
2020-01-18 21:35:18 +01:00
e72cd1468c
platforms/ac701: fix eth indent
2020-01-18 21:34:50 +01:00
908539d49f
targets/nexys4ddr: fix typo
2020-01-17 13:15:22 +01:00
bb99a8dd0c
targets/kcu105: remove main_ram_size_limit
2020-01-17 12:09:53 +01:00
84164f8fab
Copying .gitignore from LiteX repo.
2020-01-16 22:40:05 +10:00
eca9bf10ae
mimas_v7: cleanup, make it similar to others boards
2020-01-16 11:24:09 +01:00
54f39b600a
mimas_a7: fix copyrights
2020-01-16 11:02:11 +01:00
8d298951a8
Merge pull request #37 from feliks-montez/master
...
Add Mimas A7 board support
2020-01-16 11:00:32 +01:00
f9619c4a8f
aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC
2020-01-16 10:51:35 +01:00
fd1e655700
targets: cleanup EthernetSoC
2020-01-16 10:28:09 +01:00
0e6ef06494
Merge branch 'feature/add-mimas-a7-support'
2020-01-14 23:31:35 -05:00
206ec34551
platforms/mimas_a7: add support
2020-01-14 23:31:03 -05:00
9f1c3305b6
targets/mimas_a7: add support
2020-01-14 23:30:49 -05:00
223d8d832e
test_targets: add kx2
2020-01-13 17:22:49 +01:00
50d550c911
kx2: cleanup, fix copyright
2020-01-13 17:22:33 +01:00
3811b58f32
Merge pull request #36 from Marrkson/master
...
ADD: KX2 and DDR3 support
2020-01-13 17:07:16 +01:00
c109b36fb9
travis: update/fix
2020-01-13 17:00:01 +01:00
028d4a78aa
targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
2020-01-13 15:20:37 +01:00
13e5ca03a5
ADD: KX2 and DDR3 support
2020-01-13 14:21:54 +01:00
beccf670e5
hadbadge: fix _CRG
2020-01-11 10:46:23 +01:00
15f3457aea
platforms/de0nano/serial: add gpio names in comment
2020-01-10 18:53:52 +01:00
94ba343daf
targets/ac701: cpu_reset is active high
2020-01-10 18:53:14 +01:00
ab01f70e5c
platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq
2020-01-09 21:56:01 +01:00
7afe3dc674
platforms/targets: sync with litex
2020-01-09 21:10:59 +01:00
4192b20f09
targets: cleanup Altera CRGs
2020-01-09 19:46:39 +01:00
9e9fc5ef78
platforms: always use 1e9/clk_freq for default_clk_period
2020-01-09 19:28:50 +01:00
fe23881348
Merge pull request #33 from msloniewski/master
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targets/de10lite: use external clock for sys directly
2020-01-09 19:23:55 +01:00
aaf8d54c6a
targets/de10lite: use AsyncResetSynchronizer for clock domains
...
At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
2020-01-09 18:47:13 +01:00
Florent Kermarrec
Sean Cross
Paul Sajna
Tim 'mithro' Ansell
Feliks
Mark
Marcin Sloniewski