5bd8c4d74f
targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR banks (fixes Diamond build)
2019-11-01 10:52:56 +01:00
1ae26dd499
targets: use type="io" instead of io_region=True
2019-10-30 16:35:32 +01:00
8878c0a84a
versa_ecp5, trellisboard: add trellis toolchain specific arguments
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Sync up with Litex commit #49372852d.
2019-10-29 12:32:41 -04:00
5f80633154
targets: increase integrated ROM size if EthernetSoC used
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Sync up with litex commit #201218b2c.
2019-10-29 12:32:41 -04:00
c83e10d9f3
official/platforms/versa_ecp5: add serdes refclk/sma
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Sync up with litex commit #ae9c25b74.
2019-10-29 12:32:41 -04:00
91083f99a8
ulx3s: simplify SDRAM module selection
2019-10-13 21:15:22 +02:00
6f3b194bd3
Merge pull request #20 from lolsborn/ulx3s-target
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memory device selection for ulx3s
2019-10-13 20:59:16 +02:00
abf6f7b09a
memory device selection for ulx3s
2019-10-13 09:27:33 -07:00
53d5ed1226
Merge pull request #19 from lolsborn/ulx3s-target
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add sys clock freq flag, uses same method as current versa code
2019-10-13 10:32:43 +02:00
34507eb431
add sys clock freq flag, uses same method as current versa code
2019-10-13 00:44:07 -07:00
92cfd629df
partners: fomu-evt: add "dbg" connector
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This connector is for the six "debug" pins on the Raspberry Pi header.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-11 21:39:19 +08:00
09a55d20c1
partners: fomu-evt: fix spiflash4x pin mapping
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The D3 and D4 pins were swapped around, leading to interesting issues.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-11 21:38:50 +08:00
785909ac5f
targets: switch from shadow_base to io_regions
2019-10-09 11:09:59 +02:00
19e2a12266
Merge pull request #18 from xobs/fomu-cpu-updates
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Fomu cpu updates
2019-09-27 16:55:27 +08:00
c20c489d66
fomu-evt: add i2c pins
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Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-27 11:26:23 +08:00
48cd1208df
targets: sync with litex targets
2019-09-25 14:09:25 +02:00
0ead12bae8
targets/ulx3s: revert to cl=2
2019-09-25 13:58:45 +02:00
c8e8f254ca
targets: fomu: add USBSoC and default to heap placer
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The heap placer is important enough that we should just make it the
default.
Also, add a `USBSoC` that includes the required interrupt table, as this
must be specified prior to calling `__init__()`.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:08:05 +08:00
218bd353c1
targets: fomu: use memory array for sram address
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Use the memory array to find the address for the sram bank.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:07:26 +08:00
348677598d
targets: fomu: support building with a cpu
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Allow the user to specify a CPU.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-17 17:06:23 +08:00
e94c6c8f27
partner/netv2: switch to MVP (K4B2G1646F instead of MT41J128M16)
2019-09-12 09:52:13 +02:00
91feb59f49
Merge branch 'master' of http://github.com/litex-hub/litex-boards
2019-09-11 23:02:44 +02:00
a92ce32f91
targets/netv2: add clk100 (for framebuffer)
2019-09-11 23:02:21 +02:00
ec97d01feb
platforms/netv2: add spiflashx4, hdmi in/out
2019-09-11 23:01:58 +02:00
91a1520655
add initial Trenz Cyclone 10 LP RefKit support with SDRAM/HyperRAM/Ethernet
2019-09-10 11:32:29 +02:00
c6bb34d78a
partner/targets/nereid: MT8KTF51264 now in LiteDRAM
2019-09-09 08:50:06 +02:00
b4eefa6c33
import: allow importing directly from litex_boards.platforms or litex_boards.targets
2019-09-03 15:30:20 +02:00
ec5540454b
partner: aller/nereid/tagus fix copyright (Rohit Singh as main author), do some cosmetic
2019-09-02 11:43:30 +02:00
cd527f0fcb
Merge branch 'master' into master
2019-09-02 11:29:22 +02:00
d78965ffb2
partner/targets/fomu fix copyright & mode
2019-09-02 11:23:43 +02:00
bdbd2ec1c0
partner: add fomu target
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This adds the Fomu target back in. The default BaseSoC supports
various USB methods, and will be updated as more become available.
The debug bridge may optionally be added.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-02 14:18:09 +08:00
e704014b36
targets/__init__: comment targets import until we found a way to avoid litedram/liteeth dependecies for targets no using them.
2019-09-01 11:43:21 +02:00
346621b9fc
partner: add platforms and targets for aller, tagus and nereid boards
2019-09-01 03:02:04 -05:00
1131af05af
nexys_video: generate clk100
2019-08-27 14:05:07 +02:00
f661ee0ec9
targets: fix import
2019-08-26 11:00:12 +02:00
ac58d57a83
targets: import platforms from litex_boards.platforms
2019-08-26 09:09:40 +02:00
b84308cb58
list all platforms/targets in platforms.py, targets.py to ease import
2019-08-26 09:07:07 +02:00
618f41bb1e
Update ecp5_evn.py
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The system clock was driven directly while it should be driven by the PLL.
2019-08-22 02:27:50 +02:00
1abca7dcff
Turn litex_boards.community into module
2019-08-12 00:17:26 +02:00
ad21f15782
Merge pull request #10 from DurandA/ecp5-evn
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Add ECP5 Evaluation Board
2019-08-09 12:37:36 +02:00
c90950e319
Default to 60 Mhz system clock on ECP5 Evaluation Board
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Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
2019-08-09 11:58:30 +02:00
9e6dccc277
Remove ECP5 Evaluation Board programmer
2019-08-09 11:54:49 +02:00
4126ed21d5
Add X5 clock and PLL to ECP5 Evaluation Board
2019-08-09 11:54:38 +02:00
c7444fe19c
Add ECP5 Evaluation Board
2019-08-09 09:45:13 +02:00
2596b20982
partner/targets/fomu: remove for now since only has a CRG (we'll add one later with a real design)
2019-08-07 09:08:11 +02:00
0c1fa7f4a8
partner/platform/fomu: cleaup, make it similar to others platforms
2019-08-07 09:04:31 +02:00
9f3ed82097
keep up to date with LiteX
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- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
2019-08-07 08:47:08 +02:00
bbf0e770e9
partner/targets/trellisboard: cleanup/update
2019-07-12 19:39:12 +02:00
a792502756
targets: make sure all targets have copyrights & #!/usr/bin/env python3
2019-07-12 19:36:49 +02:00
e470b55d2b
fomu, trellisboard: +x
2019-07-12 19:24:08 +02:00
a88970a67f
move trellis board from community to partner
2019-07-12 19:23:21 +02:00
82d73b8359
Merge branch 'master' of http://github.com/litex-hub/litex-boards
2019-07-12 19:19:31 +02:00
debafd7c17
official/partner: update
2019-07-12 19:19:01 +02:00
a07e88d761
community: Add TrellisBoard
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-09 15:52:28 +01:00
adcc34b528
Turn litex_boards.partner into module
2019-07-01 19:36:34 +02:00
325b6399a2
add test/test_targets (only test platforms with simple target for now)
2019-06-24 12:38:58 +02:00
aeddb93729
add copyright header to all files, udpate.
2019-06-24 12:13:54 +02:00
49ffc94e85
partner: platforms: fomu_evt: rename rgb_led_n -> rgb_led
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The evt platform has a different naming scheme from the other two
versions of Fomu.
This harmonises the naming of the rgb_led pads between all of the Fomu
variants.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 19:21:15 -07:00
d01711fdf9
partner: targets: add fomu target
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The `fomu` target represents a generic target that supports the Fomu
48 MHz crystal, with or without a PLL.
It does not yet include a BaseSoC, since that requires USB and
up5kspram, neither of which are present yet.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-06-19 12:58:13 -07:00
482a00aa76
fomu: move to right location
2019-06-12 19:50:46 +02:00
44d01edab9
dispatch platforms/targets by level of support
2019-06-10 18:59:49 +02:00
4213c75e48
init repo with litex official boards
2019-06-10 17:11:36 +02:00
Florent Kermarrec
Gabriel Somlo
Steven Osborn
Sean Cross
Antti Lukats
Rohit Singh
Arnaud Durand
David Shah