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149 Commits

Author SHA1 Message Date
Florent Kermarrec eca9bf10ae mimas_v7: cleanup, make it similar to others boards 2020-01-16 11:24:09 +01:00
Florent Kermarrec 54f39b600a mimas_a7: fix copyrights 2020-01-16 11:02:11 +01:00
enjoy-digital 8d298951a8
Merge pull request #37 from feliks-montez/master 
Add Mimas A7 board support
 2020-01-16 11:00:32 +01:00
Florent Kermarrec f9619c4a8f aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC 2020-01-16 10:51:35 +01:00
Florent Kermarrec fd1e655700 targets: cleanup EthernetSoC 2020-01-16 10:28:09 +01:00
Feliks 0e6ef06494 Merge branch 'feature/add-mimas-a7-support' 2020-01-14 23:31:35 -05:00
Feliks 206ec34551 platforms/mimas_a7: add support 2020-01-14 23:31:03 -05:00
Feliks 9f1c3305b6 targets/mimas_a7: add support 2020-01-14 23:30:49 -05:00
Florent Kermarrec 223d8d832e test_targets: add kx2 2020-01-13 17:22:49 +01:00
Florent Kermarrec 50d550c911 kx2: cleanup, fix copyright 2020-01-13 17:22:33 +01:00
enjoy-digital 3811b58f32
Merge pull request #36 from Marrkson/master 
ADD: KX2 and DDR3 support
 2020-01-13 17:07:16 +01:00
Florent Kermarrec c109b36fb9 travis: update/fix 2020-01-13 17:00:01 +01:00
Florent Kermarrec 028d4a78aa targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args 2020-01-13 15:20:37 +01:00
Mark 13e5ca03a5 ADD: KX2 and DDR3 support 2020-01-13 14:21:54 +01:00
Florent Kermarrec beccf670e5 hadbadge: fix _CRG 2020-01-11 10:46:23 +01:00
Florent Kermarrec 15f3457aea platforms/de0nano/serial: add gpio names in comment 2020-01-10 18:53:52 +01:00
Florent Kermarrec 94ba343daf targets/ac701: cpu_reset is active high 2020-01-10 18:53:14 +01:00
Florent Kermarrec ab01f70e5c platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq 2020-01-09 21:56:01 +01:00
Florent Kermarrec 7afe3dc674 platforms/targets: sync with litex 2020-01-09 21:10:59 +01:00
Florent Kermarrec 4192b20f09 targets: cleanup Altera CRGs 2020-01-09 19:46:39 +01:00
Florent Kermarrec 9e9fc5ef78 platforms: always use 1e9/clk_freq for default_clk_period 2020-01-09 19:28:50 +01:00
enjoy-digital fe23881348
Merge pull request #33 from msloniewski/master 
targets/de10lite: use external clock for sys directly
 2020-01-09 19:23:55 +01:00
Marcin Sloniewski aaf8d54c6a targets/de10lite: use AsyncResetSynchronizer for clock domains 
At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
 2020-01-09 18:47:13 +01:00
Gabriel Somlo d08dfdb808 platforms/nexys4ddr: add sdcard pins (sync w. litex commit #e99740e8) 2020-01-09 09:25:19 -05:00
Florent Kermarrec babbc676eb targets: cleanup ECP5 CRGs 2020-01-09 14:24:18 +01:00
Florent Kermarrec 82601ff700 hadbadge: remove speed_grade workaround, now passed to trellis from device. 2020-01-08 19:44:35 +01:00
Florent Kermarrec 1f300bb03e add initial camlink_4k support 2020-01-08 09:56:37 +01:00
Florent Kermarrec c0e4578bea targets/hadbadge: cleanup/simplify (keep things similar to ulx3s) and add copyrights 2020-01-07 10:29:58 +01:00
Florent Kermarrec 85c4f76eba platform/hadbadge: cleanup/simplify and add copyrights 2020-01-07 10:29:01 +01:00
enjoy-digital 829898d652
Merge pull request #31 from pdp7/master 
add the Hackaday Supercon ECP5 badge
 2020-01-07 09:48:15 +01:00
enjoy-digital e9637eea60
Merge pull request #32 from DurandA/patch-2 
Update ecp5_evn.py
 2020-01-07 09:22:33 +01:00
Arnaud Durand ab41cf5b79
Update ecp5_evn.py 2020-01-07 01:55:59 +01:00
Drew Fustini b3f175c064 add the Hackaday Supercon ECP5 badge 
Add the Hackaday Supercon 2019 badge which has an ECP5 FPGA:
https://hackaday.io/project/167255-2019-hackaday-superconference-badge

These changes are from Michael Welling's fork:
https://github.com/mwelling/linux-on-litex-vexriscv

During Supercon, we trying two approaches:
- use the built-in 16MB QSPI SRAM
- use add-on cartiridge with 32MB SDRAM by Jacob Creedon

We were not able to get the QSPI SRAM working so I've removed
those changes, and I have just added the changes that are needed
to boot Linux with the 32MB SDRAM.

Thanks to Jacob Creedon, Greg Davill and Tim Ansell who helped debug.

KiCad design files for the SDRAM cartridge are available at:
https://github.com/jcreedon/dram-cart/

The SDRAM cartridge PCB is shared at:
https://oshpark.com/shared_projects/IQSl2lid

More information in this blog post:
https://blog.oshpark.com/2019/12/20/

The Hackaday Supercon badge PCB design is here:
https://github.com/Spritetm/hadbadge2019_pcb
 2020-01-06 16:59:15 +01:00
Tim Ansell f8f2301a3e
Merge pull request #30 from mithro/fomu-update 
Updating the templates for Fomu.
 2020-01-03 08:40:18 +00:00
Tim 'mithro' Ansell 250706b98c Updating the templates for Fomu. 2020-01-02 13:55:09 +00:00
Florent Kermarrec 2b43a18a3c platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv 2019-12-31 18:18:56 +01:00
Florent Kermarrec c96e7c8fb9 platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv 2019-12-31 18:07:18 +01:00
Florent Kermarrec 2259042383 pipistrello: add copyrights 2019-12-31 17:44:24 +01:00
enjoy-digital 6324433e1c
Merge pull request #28 from zakgi/master 
Adding initial support for Saanlima's Pipistrello LX45 board
 2019-12-31 17:33:25 +01:00
Florent Kermarrec 980b0ebda0 targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer) 2019-12-31 17:30:23 +01:00
Florent Kermarrec 10e5248bda targets/de10lite: minor cleanup on import/_CRG 2019-12-31 17:26:09 +01:00
enjoy-digital 9d6a6c1bcb
Merge pull request #29 from msloniewski/master 
Update de10lite platform
 2019-12-31 17:17:48 +01:00
msloniewski 9c5a4f757f targets/de10lite: add VideoSoC with VGA peripheral 
Add VideoSoC build option, based on Frank Buss example.
 2019-12-30 23:25:43 +01:00
msloniewski cace17e162 targets/de10lite: refactor setting up clock domains 
Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
 2019-12-30 23:25:43 +01:00
msloniewski 9ed68d129f platforms/de10lite: add additional configuration 
Use single image with memory initialization
to make more space for SoC ROM sector.
 2019-12-30 23:23:44 +01:00
msloniewski 28753a2c04 platforms/de10lite: remove UART pins from GPIO resource 
V10 and W10 pins were used in UART periph, causing error
when gpio_0 were requested.
 2019-12-30 23:06:58 +01:00
Tim 'mithro' Ansell 359918c2a2 Comment out template overrides for now. 2019-12-30 19:23:05 +01:00
Florent Kermarrec 1f32dcf662 partner: rename orange_crab to orangecrab 2019-12-30 12:07:34 +01:00
Florent Kermarrec 8965b01347 partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC 2019-12-30 11:54:53 +01:00
Greg Davill e77afaaef0 partner: add OrangeCrab support (https://github.com/gregdavill/OrangeCrab) 2019-12-30 11:54:45 +01:00