fd1e655700
targets: cleanup EthernetSoC
2020-01-16 10:28:09 +01:00
50d550c911
kx2: cleanup, fix copyright
2020-01-13 17:22:33 +01:00
3811b58f32
Merge pull request #36 from Marrkson/master
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ADD: KX2 and DDR3 support
2020-01-13 17:07:16 +01:00
c109b36fb9
travis: update/fix
2020-01-13 17:00:01 +01:00
028d4a78aa
targets: use default integrated rom/ram size passed with **kwargs from default soc_core_args
2020-01-13 15:20:37 +01:00
13e5ca03a5
ADD: KX2 and DDR3 support
2020-01-13 14:21:54 +01:00
beccf670e5
hadbadge: fix _CRG
2020-01-11 10:46:23 +01:00
15f3457aea
platforms/de0nano/serial: add gpio names in comment
2020-01-10 18:53:52 +01:00
94ba343daf
targets/ac701: cpu_reset is active high
2020-01-10 18:53:14 +01:00
ab01f70e5c
platforms/ac701: set internal vref to 0.750v on DDR3 banks, use IN_TERM=UNTUNED_SPLIT_50 on dq
2020-01-09 21:56:01 +01:00
7afe3dc674
platforms/targets: sync with litex
2020-01-09 21:10:59 +01:00
4192b20f09
targets: cleanup Altera CRGs
2020-01-09 19:46:39 +01:00
9e9fc5ef78
platforms: always use 1e9/clk_freq for default_clk_period
2020-01-09 19:28:50 +01:00
fe23881348
Merge pull request #33 from msloniewski/master
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targets/de10lite: use external clock for sys directly
2020-01-09 19:23:55 +01:00
aaf8d54c6a
targets/de10lite: use AsyncResetSynchronizer for clock domains
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At the start output of the pll is not stabilized, which
caused malfunctions when used for sys clock domain.
Use AsyncResetSynchronizer to start clock domains
on pll locked signal.
2020-01-09 18:47:13 +01:00
d08dfdb808
platforms/nexys4ddr: add sdcard pins (sync w. litex commit #e99740e8)
2020-01-09 09:25:19 -05:00
babbc676eb
targets: cleanup ECP5 CRGs
2020-01-09 14:24:18 +01:00
82601ff700
hadbadge: remove speed_grade workaround, now passed to trellis from device.
2020-01-08 19:44:35 +01:00
1f300bb03e
add initial camlink_4k support
2020-01-08 09:56:37 +01:00
c0e4578bea
targets/hadbadge: cleanup/simplify (keep things similar to ulx3s) and add copyrights
2020-01-07 10:29:58 +01:00
85c4f76eba
platform/hadbadge: cleanup/simplify and add copyrights
2020-01-07 10:29:01 +01:00
829898d652
Merge pull request #31 from pdp7/master
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add the Hackaday Supercon ECP5 badge
2020-01-07 09:48:15 +01:00
ab41cf5b79
Update ecp5_evn.py
2020-01-07 01:55:59 +01:00
b3f175c064
add the Hackaday Supercon ECP5 badge
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Add the Hackaday Supercon 2019 badge which has an ECP5 FPGA:
https://hackaday.io/project/167255-2019-hackaday-superconference-badge
These changes are from Michael Welling's fork:
https://github.com/mwelling/linux-on-litex-vexriscv
During Supercon, we trying two approaches:
- use the built-in 16MB QSPI SRAM
- use add-on cartiridge with 32MB SDRAM by Jacob Creedon
We were not able to get the QSPI SRAM working so I've removed
those changes, and I have just added the changes that are needed
to boot Linux with the 32MB SDRAM.
Thanks to Jacob Creedon, Greg Davill and Tim Ansell who helped debug.
KiCad design files for the SDRAM cartridge are available at:
https://github.com/jcreedon/dram-cart/
The SDRAM cartridge PCB is shared at:
https://oshpark.com/shared_projects/IQSl2lid
More information in this blog post:
https://blog.oshpark.com/2019/12/20/
The Hackaday Supercon badge PCB design is here:
https://github.com/Spritetm/hadbadge2019_pcb
2020-01-06 16:59:15 +01:00
f8f2301a3e
Merge pull request #30 from mithro/fomu-update
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Updating the templates for Fomu.
2020-01-03 08:40:18 +00:00
250706b98c
Updating the templates for Fomu.
2020-01-02 13:55:09 +00:00
2b43a18a3c
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
2019-12-31 18:18:56 +01:00
c96e7c8fb9
platforms/pipistrello: cleanup, remove extra stuff specific to litex-buildenv
2019-12-31 18:07:18 +01:00
2259042383
pipistrello: add copyrights
2019-12-31 17:44:24 +01:00
6324433e1c
Merge pull request #28 from zakgi/master
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Adding initial support for Saanlima's Pipistrello LX45 board
2019-12-31 17:33:25 +01:00
980b0ebda0
targets/de10lite: rename VideoSoC to VGASoC (to avoid confusion with VideoSoC as used on Video designs with framebuffer)
2019-12-31 17:30:23 +01:00
10e5248bda
targets/de10lite: minor cleanup on import/_CRG
2019-12-31 17:26:09 +01:00
9c5a4f757f
targets/de10lite: add VideoSoC with VGA peripheral
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Add VideoSoC build option, based on Frank Buss example.
2019-12-30 23:25:43 +01:00
cace17e162
targets/de10lite: refactor setting up clock domains
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Use PLL to generate clock for both sys clock domain and clock domain
for sdram. Additionally set up clock domain for VGA periph.
2019-12-30 23:25:43 +01:00
9ed68d129f
platforms/de10lite: add additional configuration
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Use single image with memory initialization
to make more space for SoC ROM sector.
2019-12-30 23:23:44 +01:00
28753a2c04
platforms/de10lite: remove UART pins from GPIO resource
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V10 and W10 pins were used in UART periph, causing error
when gpio_0 were requested.
2019-12-30 23:06:58 +01:00
359918c2a2
Comment out template overrides for now.
2019-12-30 19:23:05 +01:00
1f32dcf662
partner: rename orange_crab to orangecrab
2019-12-30 12:07:34 +01:00
8965b01347
partner/orange_crab: cleanup, make it similar to others targets and only keep BaseSoC
2019-12-30 11:54:53 +01:00
e77afaaef0
partner: add OrangeCrab support ( https://github.com/gregdavill/OrangeCrab )
2019-12-30 11:54:45 +01:00
39e428581f
Adding initial support for Saanlima's Pipistrello LX45 board
2019-12-29 18:29:11 -08:00
48476be9e2
aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address
2019-12-14 22:10:04 +01:00
7184032555
aller/neired/tagus: fix gateware/software build directory
2019-12-14 11:29:15 +01:00
4334ba9527
partner/aller, nereid, tagus: Remove deprecated param
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get_csr_header parameter with_shadow_base
removed/deprecated in litex 2a8d8c8f. New default
behavior matches the desired behavior in these targets.
2019-12-14 01:04:28 +00:00
3012cf75fe
partner/aller, nereid, tagus: Use updated csr APIs
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litex commit 8be5824e258b84df240d34636aaa539124b92c65 simplified the handling
of csr regions and constants.
2019-12-14 01:00:52 +00:00
d91458c3e6
targets/versa_ecp5: fix compilation with diamond
2019-12-06 16:16:19 +01:00
30ea463b41
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
2019-12-06 16:01:59 +01:00
8fa3f09226
partner/c10prefkit: apply ethernet constraints on nets as done on Xilinx devices.
2019-12-06 15:22:40 +01:00
0a56d86b1a
partner/c10lprefkit: remove FAMILY platform_command (not needed)
2019-12-06 15:21:48 +01:00
5193f7155a
partner/aller,nereid & tagus: fix compilation
2019-12-03 09:37:18 +01:00
Florent Kermarrec
Mark
Marcin Sloniewski
Gabriel Somlo
Arnaud Durand
Drew Fustini
Tim Ansell
Greg Davill
Giammarco Zacheo
Derek Kozel