00895518e5
cores/cpu: use standard+debug variant when only debug is specified.
2020-02-18 16:59:55 +01:00
ae45be4773
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
2020-02-18 10:15:01 +01:00
9baa3ad5bb
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
2020-02-18 09:13:32 +01:00
854e7cc908
integration/soc: improve Region logger
2020-02-18 08:27:59 +01:00
9cb8f68e82
bios/boot: update and fix flashboot, improve verbosity
2020-02-17 19:21:54 +01:00
6ed0f445b6
soc: increase supporteds address_width/paging
2020-02-17 08:36:40 +01:00
5b3808cb81
soc_core: expose CSR paging
2020-02-17 08:34:10 +01:00
0497f3ca71
soc/csr_bus: improve CSR paging genericity
2020-02-17 08:28:56 +01:00
351896bf57
tools/litex_sim: use new sdram verbosity parameter
2020-02-16 16:09:06 +01:00
67e8a042f8
integration/soc: add configurable CSR Paging
2020-02-16 12:32:05 +01:00
6576470179
soc_core: add back identifier
2020-02-15 19:04:47 +01:00
8f6114d0cd
Merge pull request #387 from BracketMaster/master
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litex_sim now working on MacOS and Linux
2020-02-15 17:05:50 +01:00
3da204edd6
update to work with mac
2020-02-15 10:37:39 -05:00
3574b90924
tools/litex_sim: specify default local/remote-ip addresses.
2020-02-15 14:04:44 +01:00
aebaea7764
tools/litex_sim: add ethernet local/remote-ip arguments.
2020-02-15 14:01:56 +01:00
18a9d4ff2f
interconnect/stream: cleanup imports/idents
2020-02-14 08:08:19 +01:00
57fb3720e2
Merge pull request #386 from antmicro/sdram-timing-checker
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tools/litex_sim: add cli options to control SDRAM timing checker
2020-02-13 16:53:12 +01:00
eff85a99bb
tools/litex_sim: add cli options to control SDRAM timing checker
2020-02-13 14:45:15 +01:00
e4712ff7f3
soc_core: fix cpu_variant renaming regression
2020-02-13 08:34:39 +01:00
a2f1683b97
doc: rename lxsocdoc -> socdoc and update readme
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With the merge of lxsocdoc into upstream litex, the old name of
"lxsocdoc" doesn't make as much sense. Additionally, the import paths
are now different.
Rename this file to reflect the new home of `soc/doc`, and update the
code examples to work with the new name.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-13 08:47:58 +08:00
baa29f1b03
doc: fix regression with new irq manager
...
Previously, we were accessing the `soc.soc_interrupt_map` property in
order to be able to enumerate the interrupts. This has been subsumed
into a more general `irq` object that manages the interrupts.
Use `soc.irq.locs` instead of `soc.soc_interrupt_map` as the authority
on interrupts for both doc and export.
This fixes #385 .
Signed-off-by: Sean Cross <sean@xobs.io>
2020-02-13 08:32:44 +08:00
1620f9c5b0
soc/CSR: show alignment in report and add info when updating.
2020-02-12 21:55:30 +01:00
5b34f4cd34
soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket
2020-02-12 21:25:52 +01:00
2f69f607e3
integration/soc: fix refactoring issues
2020-02-12 18:16:38 +01:00
1d6ce66bf7
soc/integration/builder: update copyright, align arguments
2020-02-12 16:43:11 +01:00
98ae91ada5
Merge pull request #383 from Xiretza/builder-directories
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Unify output directory handling in builder
2020-02-12 16:38:04 +01:00
b56545791c
Unify output directory handling in builder
2020-02-12 15:47:16 +01:00
4a15c3e219
Merge pull request #382 from enjoy-digital/new_soc
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Add new SoC/LiteXSoC classes and use it for SoCCore/SoCSDRAM
2020-02-11 18:39:33 +01:00
e9c665a539
soc_core/soc_sdram: add disclaimer
2020-02-11 18:28:05 +01:00
5558865cbf
soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region
2020-02-11 18:21:41 +01:00
1b5caf56fb
soc: fix busword typo
2020-02-11 17:57:05 +01:00
8b5cc34553
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:44:24 +01:00
240a55bace
Merge branch 'master' into new_soc
2020-02-11 17:22:06 +01:00
d5ad1d56f2
soc/integration: move mem_decoder to soc_core
2020-02-11 17:19:22 +01:00
0a737cb624
soc/integration/common: simplify get_version
2020-02-11 17:16:24 +01:00
399b65fa17
soc/add_uart: fix bridge
2020-02-11 16:55:37 +01:00
160c55d1d4
soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted)
2020-02-11 16:44:25 +01:00
b2c66b1efd
soc: avoid double definition of main_ram
2020-02-11 16:39:37 +01:00
5f9946085b
soc: improve log colors on error reporting
2020-02-11 16:24:57 +01:00
b22d2ca02b
soc: add linker regions management
2020-02-11 15:28:02 +01:00
abc31a92c6
soc: improve log presentation/colors
2020-02-11 14:50:16 +01:00
91e2797bb4
soc: fix cpu_reset_address
2020-02-11 14:17:32 +01:00
0d7430fc69
tools/litex_sim_new: remove
2020-02-11 14:05:01 +01:00
21d38701df
soc: fix build_time format
2020-02-11 13:23:53 +01:00
4d761e1afd
cores/cpu: remove separators on io_regions (requires python 3.6)
2020-02-11 13:12:54 +01:00
7c57a33ba0
Merge pull request #380 from Xiretza/cpunone-all-io
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Allow all memory regions to be used as IO with CPUNone
2020-02-11 13:11:33 +01:00
b43d830fda
soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices)
2020-02-11 09:30:45 +01:00
ea8e745ac2
soc_core/common: move old mem_decoder to soc_core, simplify get_version
2020-02-11 08:44:23 +01:00
e301df7f56
Allow all memory regions to be used as IO with CPUNone
2020-02-10 19:56:36 +01:00
16d1972bf8
integration/common: fix mem_decoder (shadow base has been deprecated)
2020-02-10 19:40:56 +01:00
Florent Kermarrec
Yehowshua Immanuel
Piotr Binkowski
Sean Cross
Xiretza