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91 Commits

Author SHA1 Message Date
Florent Kermarrec 796119fcaf global: pep8 (E203) 2015-04-13 16:53:07 +02:00
Florent Kermarrec ca7019fa0d global: pep8 (E231) 2015-04-13 16:51:00 +02:00
Florent Kermarrec 9ad90b531e global: pep8 (E201) 2015-04-13 16:48:51 +02:00
Florent Kermarrec f68423f423 global: pep8 (E302) 2015-04-13 16:47:22 +02:00
Florent Kermarrec d9e09707ae global: pep8 (replace tabs with spaces) 2015-04-13 16:19:55 +02:00
Florent Kermarrec 2040727179 litesata: more pep8 (when convenient), should be almost OK 2015-04-13 16:09:04 +02:00
Florent Kermarrec 1f19e6ae92 litesata: pep8 (E265) 2015-04-13 15:58:58 +02:00
Florent Kermarrec c8bcbfb855 litesata: pep8 (E261, E271) 2015-04-13 15:51:17 +02:00
Florent Kermarrec 2e5501933a litesata: pep8 (W292) 2015-04-13 15:44:52 +02:00
Florent Kermarrec ea67080462 litesata: pep8 (E225) 2015-04-13 15:44:04 +02:00
Florent Kermarrec a9b42161c0 litesata: pep8 (E222) 2015-04-13 15:29:34 +02:00
Florent Kermarrec 77cdb953ad litesata: pep8 (E401) 2015-04-13 15:27:36 +02:00
Florent Kermarrec 8f7751e412 litesata: pep8 (E203) 2015-04-13 15:25:40 +02:00
Florent Kermarrec 61fa72b655 litesata: pep8 (E231) 2015-04-13 15:19:34 +02:00
Florent Kermarrec d0c5bd377a litesata: pep8 (E302) 2015-04-13 15:12:39 +02:00
Florent Kermarrec 808e1fe866 litesata: pep8 (replace tabs with spaces) 2015-04-13 14:59:00 +02:00
Robert Jordens d6c19858fa s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE 2015-04-10 16:12:29 +08:00
Florent Kermarrec ea613cd8ee litesata: update build core target generation 2015-04-09 00:00:25 +02:00
Florent Kermarrec 03aa972bb6 lite*: finish ModuleTransformer adaptations (need to be tested on board) 2015-04-08 23:27:22 +02:00
Robert Jordens 66f8dcbfaf lite*: adapt to new ModuleTransformer semantics 
NOTE: There is loads of duplicated code between the lite*
modules that should be shared.
 2015-04-04 19:17:24 +08:00
Sebastien Bourdeauducq 382ed013af minor cleanups 2015-04-02 14:40:29 +08:00
Florent Kermarrec 60124be293 adapt LiteSATA to new SoC 2015-04-01 22:52:19 +02:00
Sebastien Bourdeauducq 6e2a662dd7 litesata: adapt to new SoC API 2015-04-01 17:37:53 +08:00
Florent Kermarrec b313772a0c sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0) 2015-03-29 12:34:40 +02:00
Florent Kermarrec a8d91c0c1d sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue) 2015-03-28 16:35:15 +01:00
Florent Kermarrec 75ee8a5db9 sdram/phy/simphy: OK with DDR3 2015-03-28 01:59:55 +01:00
Florent Kermarrec 51ce7cad6f sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2 2015-03-28 01:18:35 +01:00
Florent Kermarrec a95b3f8f13 sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it) 2015-03-28 01:17:50 +01:00
Florent Kermarrec 7fe748e1b0 sdram/module: clean up tREFI. (use 64ms/8k or 4k) 2015-03-28 01:09:21 +01:00
Florent Kermarrec 9137b91e9e sdram: remove nbits from modules and databits from GeomSettings 2015-03-26 23:27:37 +01:00
Florent Kermarrec 9a9af17aca sdram/phy/simphy: remove use of iter 2015-03-26 23:02:23 +01:00
Florent Kermarrec e6de4b1bf9 sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16) 2015-03-26 22:28:32 +01:00
Florent Kermarrec 257706517e software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation 2015-03-26 00:01:42 +01:00
Florent Kermarrec ff11cb97a9 sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True 2015-03-25 17:22:26 +01:00
Florent Kermarrec ba8b24df57 sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00
Florent Kermarrec 7ea9e2ba89 sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-25 16:56:29 +01:00
Florent Kermarrec 92f81409f2 sdram/module: fix tREFI on AS4C16M16 2015-03-22 03:20:02 +01:00
Florent Kermarrec 30c2521eb0 sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00
Florent Kermarrec 70469e1f37 sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit) 2015-03-21 21:32:39 +01:00
Florent Kermarrec c60d99583d sdram/module: add tREFI uniformization to TODO 2015-03-21 18:59:16 +01:00
Florent Kermarrec 0f9b0c6f0f sdram/module: add MT47H128M8 DDR2 (used for a customer) 2015-03-21 18:52:10 +01:00
Florent Kermarrec 45eb5090db sdram/module: add speedgrate note for IS42S16160 and AS4C16M16 2015-03-21 18:41:59 +01:00
Florent Kermarrec a560ba35bd sdram/module: add AS4C16M16 for minispartan6 2015-03-21 18:38:53 +01:00
Florent Kermarrec 854058a8db sdram/module: add description and TODO list 2015-03-21 17:44:04 +01:00
Florent Kermarrec 52924ee1f2 sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705 2015-03-21 17:25:36 +01:00
Florent Kermarrec fd2f8d4bb4 sdram: define MT46V32M16 and use it on m1/mixxeo 2015-03-21 17:04:58 +01:00
Florent Kermarrec de2f1c31d5 sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
Florent Kermarrec 6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
 2015-03-21 12:55:39 +01:00
Florent Kermarrec 9107710f03 litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
Florent Kermarrec 236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00