Dolu1990
1267ba8ae6
Update Nax/Vexii
2024-07-10 09:35:34 +02:00
Dolu1990
372ab25273
Merge branch 'nax64_irq' into vexiiriscv
2024-07-09 15:18:25 +02:00
Dolu1990
28d4aff10f
vexii non coherent config write bandwidth improvment
2024-06-13 23:20:25 +02:00
Dolu1990
2e4813d6ae
Fix vexii axi3
2024-06-12 19:33:20 +02:00
Dolu1990
8bb10e1617
cpu/vexii: Add AXI3 support via --with-axi3
2024-06-12 11:25:18 +02:00
Dolu1990
8c80a6c19c
linux dts: rework "rocket" in cpu_name into cpu_name == "rocket"
2024-06-11 13:08:25 +02:00
Dolu1990
87ae5db16b
linux dts: add vexii clint support
2024-06-10 18:10:13 +02:00
Dolu1990
f0b0d8db29
linux dts: add vexii clint support
2024-06-10 17:02:00 +02:00
Dolu1990
9c202b59d1
Fix axi id width
2024-06-07 18:33:05 +02:00
Dolu1990
bd96b47041
Vexii fix mem data width
2024-06-06 16:36:56 +02:00
Dolu1990
0e04949485
vexii fix l1 cache size
2024-06-06 13:50:27 +02:00
Dolu1990
9165886525
snyc
2024-05-28 12:59:27 +02:00
Dolu1990
2dac84f32c
vexii l2 now support self flush. ex :
...
--l2-self-flush=40c00000,40DD4C00,1666666
2024-05-27 17:37:30 +02:00
Dolu1990
4a6efa47c1
Add variants to VexiiRiscv
2024-05-23 16:44:20 +02:00
Dolu1990
06bbbe78e4
vexii/naxii fix floating axi wires
2024-05-20 08:56:38 +02:00
Dolu1990
21e0ec7f98
vexii/naxii fix floating axi wires
2024-05-20 08:55:05 +02:00
Dolu1990
5eeb999694
update vexii
2024-05-18 16:59:27 +02:00
Dolu1990
8c0f5447ed
fix nax/vexii git checkout process, thanks JoyBed
2024-05-18 10:01:29 +02:00
Dolu1990
0720ffb404
Update vexii
2024-05-17 10:00:24 +02:00
Dolu1990
122e060a5e
update vexii
2024-05-16 19:30:15 +02:00
Dolu1990
74b300597b
cpu/naxriscv: fix 64 bits IRQ support
2024-05-16 18:59:40 +02:00
Dolu1990
60b0273eda
Add baremetal IRQ support
2024-05-16 18:58:16 +02:00
Dolu1990
57f74da8d8
Merge branch 'master' into vexiiriscv
2024-05-16 16:17:21 +02:00
enjoy-digital
d7b4c7bc9c
Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs
...
Add baremetal IRQ support to VexRiscv-SMP and NaxRiscv.
2024-05-16 10:55:12 +02:00
Florent Kermarrec
fbf03ec74c
inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it.
...
Also cleanup self.mem.get_port call.
2024-05-16 10:36:44 +02:00
Florent Kermarrec
c0d9224f09
integration/export/_generate_csr_header_includes_c: Fix refactoring issue and do not include generated/soc.h when access functions are disabled.
2024-05-16 09:19:18 +02:00
Dolu1990
d4c1a10817
cores/cpu/naxriscv: Add baremetal IRQ support
2024-05-14 14:57:29 +02:00
Florent Kermarrec
e03b097e8e
software/libbase/isr.c: Simplify using __riscv_plic__ define.
2024-05-14 14:47:01 +02:00
Florent Kermarrec
c79e1ef95f
cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag.
2024-05-14 14:43:57 +02:00
Dolu1990
786c929f08
cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE
2024-05-14 14:24:37 +02:00
enjoy-digital
8a83585b85
Merge pull request #1953 from enjoy-digital/export_csr_c_rework
...
Simplify/Cleanup C exports and disable Fields accessors generation by default.
2024-05-14 12:54:48 +02:00
Florent Kermarrec
8eaa53ae9a
test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated).
2024-05-14 12:53:09 +02:00
enjoy-digital
c810b89464
Merge pull request #1951 from nuntipat/update-cv32e40p
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Update CV32E40P to be based on the OpenHW Group's repo
2024-05-14 12:11:50 +02:00
enjoy-digital
9b6e231a1a
Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p
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Fix CSR register definition for the CV32E41P core
2024-05-14 12:08:42 +02:00
Florent Kermarrec
46911d5078
soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects).
2024-05-14 11:59:13 +02:00
Florent Kermarrec
2574cc1ddc
integration/export: Fix read_function refactoring.
2024-05-14 11:55:34 +02:00
Dolu1990
7b7334fc17
cpu/vexiiriscv update
2024-05-14 11:41:21 +02:00
Florent Kermarrec
29bb397bb6
soc/integration/export: Add parameter to enable/disable fields access function generation.
...
Fields access function have been contributed and probably used by a few project but not really
by LiteX projects or cores itselves.
This generates complex code and compilation warnings, so it can be useful to disable them by default (but still allow used to enable them).
2024-05-14 11:22:46 +02:00
Florent Kermarrec
9f4bd5cec8
integration/export: Split get_csr_header in simpler functions.
2024-05-14 11:00:41 +02:00
Florent Kermarrec
c42cc350c6
integration/export: Split _get_rw_functions_c in simpler functions.
2024-05-14 10:47:38 +02:00
Florent Kermarrec
3506a5e82d
cores/cpu/vexriscv_smp: Prepare IRQ support based on Rocket IRQ support (not yet working).
2024-05-14 10:04:13 +02:00
Florent Kermarrec
49897ee018
software/libbase/isr.c: Cleanup plic_init/isr and move PLIC_EXT_IRQ_BASE to cores/cpu/../irq.h since specific to each CPU.
2024-05-14 10:02:56 +02:00
Nuntipat Narkthong
b0acf6136e
Fix CSR register definition for the CV32E41P core
2024-05-13 20:03:16 -04:00
Nuntipat Narkthong
41564cc47b
Update CV32E40P to be based on the OpenHW Group's repo
2024-05-13 19:59:42 -04:00
Florent Kermarrec
2613ae606a
interconnect/packet/Status: Simplify logic.
2024-05-13 17:52:24 +02:00
Florent Kermarrec
8b175c2575
CHANGES: Update.
2024-05-13 16:33:11 +02:00
enjoy-digital
0d3a8220dd
Merge pull request #1948 from Liamolucko/riscv-triples
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Add missing 32-bit variants of RISC-V target triples
2024-05-07 15:15:09 +02:00
enjoy-digital
b61e8b5d42
Merge pull request #1945 from Nicolas-Gaudin/master
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Support isr for cv32e41p core
2024-05-07 15:13:44 +02:00
enjoy-digital
e4cfe87109
Merge pull request #1946 from nrndda/AXILite_LitexXModule_revert
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Revert LitexModule for AXILiteSRAM as well.
2024-05-07 15:10:55 +02:00
Dolu1990
588b7a9519
Update Vexii
2024-05-06 19:48:56 +02:00
