d628c147ec
Sort constants in csr generation.
...
Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.
With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
CSR=software/include/generated/csr.h
for i in 1 2 3 4 5 6; do
rm -f $CSR; python make.py build-headers
cp $CSR $CSR.$i
done
md5sum $CSR.*
```
2015-09-27 11:04:28 +08:00
4fe0f6017c
Revert "Use shutil rather then rm -rf command."
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This reverts commit d8fd4fe725
2015-09-26 21:55:11 +08:00
a186bfe0f3
Revert "Use shutil rather then rm -rf command."
...
This reverts commit d8fd4fe725
2015-09-26 21:54:19 +08:00
27b2383607
sdram working on PPro
2015-09-26 21:51:22 +08:00
67133f3542
replace flen with len
2015-09-26 18:50:11 +08:00
da425d1bcb
add stream, fix CPUs and more imports. simple target boots on ppro.
2015-09-26 16:44:21 +08:00
75ef2f9004
fix most imports
2015-09-25 18:43:20 +08:00
f69674e89c
interconnect: add bus/bank components from Migen
2015-09-24 20:48:18 +08:00
ecdc4101b4
lasmicon: enable refresh at all times
2015-09-24 16:01:08 +08:00
9b08b037e4
break down sdram, improve consistency of core names
2015-09-24 15:59:55 +08:00
0f410e45f1
cores directory
2015-09-24 09:05:10 +08:00
83509163df
reorganization WIP: flatten core structure (SDRAM still needs to be done)
2015-09-24 00:18:27 +08:00
01be953e30
setup: cleanup
2015-09-23 09:52:12 +08:00
030998658d
setup: convert to unix eols
2015-09-23 09:50:31 +08:00
74b3e16dd0
CONTRIBUTING.md->rst
2015-09-23 00:57:36 +08:00
82236d9b40
migen.fhdl.std -> migen
2015-09-23 00:36:47 +08:00
bd74d39338
misoclib -> misoc
2015-09-23 00:35:02 +08:00
71993edae4
Add init file in sdram/phy dir
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Without __init__.py file, when using setup.py, setuptools' find_package() function does not find the files in sdram/phy package. Hence .egg file entirely misses sdram/phy directory
More info here: https://bitbucket.org/pypa/setuptools/issues/97
2015-09-21 23:46:16 +08:00
b2a4eead0c
uart/software: remove litescope dependency
2015-09-21 09:04:59 +02:00
bc1450e4f2
Adding --help option to flterm.
2015-09-21 11:02:36 +08:00
31956de790
dvisampler/edid: fix sda sampling, needs to be similar to scl.
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Video sources with high scl frequency were not able to access EDID information through I2C.
I2C start was not detected correctly and was randomly reseting the fsm during transfers.(seen with litescope)
2015-09-10 20:51:10 +02:00
12f5858850
Allow installing tools to a prefix.
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(Defaults to /usr/local.)
2015-09-08 08:16:34 -07:00
40f47f447a
create liteethmini and move liteeth to a separate repo ( https://github.com/enjoy-digital/liteeth )
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LiteEthMini is a subset of LiteEth intended to be used with a CPU and a software stack.
2015-09-08 01:33:57 +02:00
3f5d475b7b
remove litepcie_phy_wrappers submodule
2015-09-07 13:20:16 +02:00
5301a1776d
targets: remove USBSoC from minispartan6 (example available here: https://github.com/enjoy-digital/scarab-soc )
2015-09-07 12:47:40 +02:00
8e8cc8e5a6
move liteusb to a separate repo ( https://github.com/enjoy-digital/liteusb )
2015-09-07 12:44:47 +02:00
e49a3c20c8
move litesata to a separate repo ( https://github.com/enjoy-digital/litesata )
2015-09-07 12:27:40 +02:00
bbeb8a466d
move litescope to a separate repo ( https://github.com/enjoy-digital/litescope )
2015-09-07 12:04:04 +02:00
35e3853f6e
move litepcie to a separate repo ( https://github.com/enjoy-digital/litepcie )
2015-09-07 11:11:43 +02:00
bedf3ed9a6
misoclib/soc: fix add_constant when used for strings
2015-09-01 16:57:50 +02:00
a4808ace6f
litecores: remove unneeded AutoCSR inheritance in example designs (thanks William D. Jones)
2015-08-26 22:36:48 +02:00
e91ce85cfd
litescope/core/port: fix missing self.comb...
2015-08-24 20:12:39 +02:00
27b1dd7d9e
litescope/core/port: fix EdgeDetector CSRs names
2015-08-24 19:40:53 +02:00
fd31e6ae61
litescope/core/port: fix LiteScopeEdgeDetector (refactoring issues)
2015-08-24 18:23:38 +02:00
f3d68a54d5
liteth/phy: simplify clk_freq in LiteEthPHY autodetect function (thanks Sebastien)
2015-08-22 16:30:42 +02:00
a1e4183b3f
sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY
2015-08-22 12:50:41 +02:00
de87d65f68
sdram/module: add P3R1GE4JGF DDR2 (Atlys) and MT41J128M16 DDR3 (Opsis, Novena) modules.
2015-08-22 12:42:44 +02:00
50e857e99c
sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies.
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Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock.
Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).
2015-08-22 12:17:48 +02:00
8bb30a8620
liteeth/phy: fix autodetect (clk_freq not necessary passed in kwargs)
2015-08-22 12:08:49 +02:00
158fbe49ac
sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata_en (the controller already manages that)
2015-08-22 11:47:26 +02:00
b8f3fd53f1
README: small update
2015-08-22 11:39:54 +02:00
4acab79987
sdram/module: cleanup indent
2015-08-20 22:15:06 +02:00
63538a7d04
litecores: add -Ob option to make.py (allow to build with yosys for example)
2015-08-19 01:17:37 +02:00
3d3cd128d8
liteeth/phy: only use clk_freq for LiteEthPHYGMIIMII in autodetect
2015-08-19 01:17:35 +02:00
6683485841
tools/flterm: replace int(a, 16) with int(a, 0) for --kernel-adr
2015-08-18 15:47:09 +02:00
a9d40e790c
tools/flterm.py: cleanup kernel-adr argument parsing
2015-08-13 13:25:02 +02:00
d8fd4fe725
Use shutil rather then rm -rf command.
2015-08-13 14:54:58 +08:00
eeda704462
Use shell for globbing in clean.
2015-08-13 14:54:58 +08:00
d00e774986
All commands run should be checked.
2015-08-13 14:54:58 +08:00
5a3f4e4179
tools/flterm.py: some cleanup and fix last frame data that was not transmitted
2015-08-12 11:41:08 +02:00
Tim 'mithro' Ansell
Sebastien Bourdeauducq
Rohit Kumar Singh
Florent Kermarrec