Joe Britton
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a1e3fb16ac
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flterm.py: use serial_for_url
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2015-06-26 11:40:33 +02:00 |
Florent Kermarrec
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04c64eb1d8
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litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
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2015-06-26 00:20:58 +02:00 |
|
enjoy-digital
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c615b50735
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Merge pull request #14 from olofk/misc_fixes
Misc fixes
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2015-06-25 23:59:42 +02:00 |
Olof Kindgren
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52e6bf6987
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litesata/test: Add missing dependency on scrambler in bist_tb
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2015-06-26 01:20:25 +02:00 |
|
Olof Kindgren
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ffb6081720
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litesata/example_designs: Add missing clock in phy instantiation
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2015-06-26 01:20:25 +02:00 |
|
Florent Kermarrec
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125432b5b6
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liteeth/example_designs: use new Keep SynthesisDirective
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2015-06-23 16:15:28 +02:00 |
|
Florent Kermarrec
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351e654e9d
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software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)
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2015-06-23 09:01:34 +02:00 |
Robert Jordens
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2150e6cfef
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pipistrello: run at 83+1/3 MHz, cleanup CRG
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2015-06-22 18:56:57 -06:00 |
|
Florent Kermarrec
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01c5051866
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liteeth/software: fix wishbone bridge
|
2015-06-23 01:48:45 +02:00 |
|
Florent Kermarrec
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369cf4c4d7
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liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection
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2015-06-23 01:08:49 +02:00 |
|
Florent Kermarrec
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5c939b85ef
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liteeth/core/arp: fix table timer (wait_timer adaptation issue)
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2015-06-23 00:25:26 +02:00 |
|
Florent Kermarrec
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a3c0e5c4d9
|
liteeth/core/arp: fix missing MAC address in ARP reply
|
2015-06-22 23:15:00 +02:00 |
|
Florent Kermarrec
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781869d6f9
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software/libbase/system: fix flush_l2_cache
|
2015-06-19 09:00:14 +02:00 |
|
Florent Kermarrec
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f44956bfca
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soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
|
2015-06-19 08:39:37 +02:00 |
Sebastien Bourdeauducq
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7c2d0fa641
|
indentation
|
2015-06-17 08:32:17 -06:00 |
|
Florent Kermarrec
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c0bc94ca1c
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soc/sdram: add capability to share L2 cache in multi-CPU SoCs
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2015-06-17 15:48:45 +02:00 |
|
Florent Kermarrec
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3b9f287bab
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sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
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2015-06-17 15:30:30 +02:00 |
|
Florent Kermarrec
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a1f7ecc8c5
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litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
|
2015-06-10 12:15:59 +02:00 |
|
Florent Kermarrec
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571ce5791a
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litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
|
2015-06-10 12:14:48 +02:00 |
|
Florent Kermarrec
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1bb2580779
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sdram: use new Migen Converter in Minicon frontend and small cleanup
|
2015-06-02 19:37:08 +02:00 |
|
Florent Kermarrec
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f96a856c97
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sdram/phy: fix simphy memory usage
|
2015-06-02 19:33:09 +02:00 |
|
Florent Kermarrec
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f40140dba5
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sdram: refactor minicon and fix issues with DDRx memories
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
|
2015-05-29 12:31:56 +02:00 |
Yann Sionneau
|
a8b9c126cd
|
spiflash: now using 64k sectors
|
2015-05-27 18:44:14 +08:00 |
|
Yann Sionneau
|
3f7e161867
|
spiflash: cleanup unnecessary parenthesis
|
2015-05-27 18:44:14 +08:00 |
|
Sebastien Bourdeauducq
|
d50bb8c55e
|
litesata: more doc fixes
|
2015-05-26 14:13:13 +08:00 |
|
Sebastien Bourdeauducq
|
1e47cfce2b
|
Merge branch 'master' of https://github.com/m-labs/misoc
Conflicts:
misoclib/mem/litesata/doc/source/docs/frontend/index.rst
|
2015-05-26 13:57:26 +08:00 |
|
Sebastien Bourdeauducq
|
a9da892b57
|
litesata: doc fixes
|
2015-05-26 13:54:31 +08:00 |
|
Florent Kermarrec
|
989d8a7c29
|
liteata: fix spelling & mistakes in doc
|
2015-05-26 07:37:09 +02:00 |
|
Florent Kermarrec
|
eb922f6ddc
|
litesata: rework frontend doc and add striping, mirroring
|
2015-05-25 14:04:37 +02:00 |
|
Florent Kermarrec
|
0d1a7b9315
|
litesata: add mirroring
|
2015-05-25 14:03:14 +02:00 |
|
Florent Kermarrec
|
c3716296ae
|
litesata/examples_designs: add striping
|
2015-05-25 14:02:02 +02:00 |
|
Florent Kermarrec
|
0d2db23603
|
litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)
|
2015-05-25 13:55:15 +02:00 |
|
Florent Kermarrec
|
cb053dc011
|
liteusb/core/packet: fix missing ,
|
2015-05-25 13:53:02 +02:00 |
|
Florent Kermarrec
|
1bb5a05488
|
litesata: add striping module for use of multiple HDDs.
|
2015-05-23 14:12:20 +02:00 |
|
Florent Kermarrec
|
5daba9af68
|
litesata: do some cleanup and prepare for RAID
|
2015-05-23 14:08:56 +02:00 |
|
Florent Kermarrec
|
d9b15e6ef6
|
cores: replace Timeout with new WaitTimer
|
2015-05-12 16:14:38 +02:00 |
|
Florent Kermarrec
|
a99aa9c7fd
|
uart: rename wishbone to bridge
|
2015-05-09 16:24:28 +02:00 |
|
Florent Kermarrec
|
fb5397aa82
|
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
|
2015-05-09 16:08:20 +02:00 |
|
Florent Kermarrec
|
1fd189512f
|
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
|
2015-05-08 23:10:08 +02:00 |
|
Florent Kermarrec
|
4d902b578c
|
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
|
2015-05-07 20:03:12 +02:00 |
|
Florent Kermarrec
|
d9111f6a04
|
litesata: fix packets figure in frontend doc
|
2015-05-07 11:06:05 +02:00 |
|
Sebastien Bourdeauducq
|
566d973049
|
README: add note about submodules
|
2015-05-07 16:29:30 +08:00 |
|
Florent Kermarrec
|
5516a49696
|
litesata: add doc for frontend
|
2015-05-06 03:57:07 +02:00 |
|
Florent Kermarrec
|
6908ddbaf9
|
litesata: cleanup README/doc
|
2015-05-06 02:02:22 +02:00 |
|
Florent Kermarrec
|
7bdcbc94cd
|
litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.
Works fine @ 3Gbps, still not working @6.0Gbps
|
2015-05-06 01:33:02 +02:00 |
|
Sebastien Bourdeauducq
|
5d5d5edfe2
|
spiflash: fix miso bitbang with large DQ
|
2015-05-06 00:05:25 +08:00 |
|
Florent Kermarrec
|
553262bcc1
|
soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...
|
2015-05-04 12:28:49 +02:00 |
|
Florent Kermarrec
|
438a0856c5
|
misoclib/cpu: merge git.py in identifier
|
2015-05-02 18:42:33 +02:00 |
|
Florent Kermarrec
|
da711ad5f1
|
liteusb: add simple example design with wishbone bridge and software to control it
|
2015-05-02 18:21:18 +02:00 |
|
Florent Kermarrec
|
c98bd9fd79
|
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)
|
2015-05-02 17:07:58 +02:00 |