Sebastien Bourdeauducq
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d554a06eba
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interconnect/wishbone: fix CSRBank init
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2015-11-03 18:45:23 +08:00 |
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Sebastien Bourdeauducq
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2520ab480b
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wishbone: add read/write simulation methods
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2015-11-03 10:37:31 +08:00 |
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Sebastien Bourdeauducq
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ca9631f7d3
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interconnect/stream: add Converter (needs cleanup)
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2015-11-01 22:15:28 +08:00 |
Florent Kermarrec
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c38d8175b7
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interconnect/stream: add missing part of Demultiplexer
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2015-10-05 00:10:55 +02:00 |
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Sebastien Bourdeauducq
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617c6ecb47
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interconnect/stream: add multiplexer and demultiplexer
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2015-09-30 19:43:51 +08:00 |
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Sebastien Bourdeauducq
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b3d5d1628c
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interconnect/stream: remove param, do not depend on FIFO Record support
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2015-09-30 16:40:34 +08:00 |
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Sebastien Bourdeauducq
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b1a90053f5
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minor fixes
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2015-09-29 10:19:00 +08:00 |
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Sebastien Bourdeauducq
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67133f3542
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replace flen with len
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2015-09-26 18:50:11 +08:00 |
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Sebastien Bourdeauducq
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da425d1bcb
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add stream, fix CPUs and more imports. simple target boots on ppro.
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2015-09-26 16:44:21 +08:00 |
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Sebastien Bourdeauducq
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75ef2f9004
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fix most imports
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2015-09-25 18:43:20 +08:00 |
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Sebastien Bourdeauducq
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f69674e89c
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interconnect: add bus/bank components from Migen
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2015-09-24 20:48:18 +08:00 |
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Sebastien Bourdeauducq
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9b08b037e4
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break down sdram, improve consistency of core names
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2015-09-24 15:59:55 +08:00 |