21ad435def
Include the ethernet related header files conditionally
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Only including those header files in the litex firmware is the first step to
move the firmware parts of liteeth to the liteeth tree.
2018-01-16 14:33:49 +11:00
d37cf226d6
Merge pull request #47 from felixheld/indentation-fixes
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Fix all remaining indentation issues in python code
2018-01-13 13:29:29 +11:00
6318a2b29a
Fix all remaining indentation issues in python code
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I ran a script that shouldn't have missed any tab in the python source files.
2018-01-13 13:19:36 +11:00
782711e5a9
bios/sdram: make read leveling robust for KUS SDRAM
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Increases the initial delay step into the valid read window as
with the original delay I was not getting out of the noisy
transition window, as evidenced by seeing read delay windows
of only 8 LSB ~10% of the time, leading to failing memory
tests
2018-01-12 19:23:08 +01:00
5c95c8ead0
Merge pull request #44 from felixheld/nexys_video-dram-fix
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Fix DDR3 on nexys_video
2018-01-12 14:08:03 +11:00
c2c622691c
Merge pull request #45 from felixheld/arty-ddr3-fix
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fix DDR3 on arty
2018-01-12 14:07:32 +11:00
9eb1beea04
fix DDR3 on arty
2018-01-12 13:54:10 +11:00
4a3454107a
fix DDR3 on nexys_video
2018-01-12 13:33:13 +11:00
7b6ba372c8
Merge pull request #43 from felixheld/programmer-error-fix
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fix the unsupported programmer case for kc705 and minispartan6
2018-01-11 08:21:46 +01:00
23585385c0
fix the unsupported programmer case for kc705 and minispartan6
2018-01-11 18:15:11 +11:00
b2beec267b
Merge pull request #42 from felixheld/requirements-fix
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add pyserial to the package requirements
2018-01-11 17:46:21 +11:00
99cf4d9f26
add pyserial to the package requirements
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litex_term requires pyserial
2018-01-11 17:43:16 +11:00
10000eb607
build/xilinx/vivado: only generate constraints that are not empty
2018-01-08 17:03:19 +01:00
5681a3c1a9
bios/sdram: revert capability to do manual read leveling since still needed with some targets
2018-01-08 12:04:33 +01:00
03eb137449
bios/sdram: fix data error reporting
2018-01-08 11:43:49 +01:00
22ff745027
bump year
2018-01-08 11:43:13 +01:00
ee6b33e9d3
build: add Inverted property to IOs to ease inverting signals and propagate property to cores
2018-01-06 01:33:02 +01:00
621aaf6988
soc/integration/soc_core: avoid removing uart interrupts (break some designs)
2017-12-30 18:41:49 +01:00
377af99678
Merge pull request #40 from mithro/or1k-linux
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cpu: Adding "variant" support.
2017-12-30 11:19:12 +01:00
f8a07c5d3c
Merge pull request #41 from cr1901/python-3.6
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fhdl/tracer: Import Python 3.5/3.6 version guards from Migen.
2017-12-30 11:17:41 +01:00
ff0ad9a622
fhdl/tracer: Import Python 3.5/3.6 version guards from Migen.
2017-12-29 19:56:52 -05:00
44650dffd8
cpu: Adding "variant" support.
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It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.
For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.
Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
2017-12-30 01:18:51 +01:00
2cc6a3036c
Merge pull request #39 from mithro/master
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Wait longer before giving up on the 2nd tftp block.
2017-12-29 23:57:42 +01:00
bbd15ca567
Wait longer before giving up on the 2nd tftp block.
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Previously we would wait the same number of iterations as it took us to
receive the first data block after sending the request. When using the
build in tftp server in qemu, the first wait loop succeeds (and thus
breaks when 'i' is still 0.
Since the counter was never reset between the first and second data
block, under qemu the tftp_get call would fail before ever checking if
we have received the second block of data.
Now that we initialise 'i' to 12M, we ensure that we wait the same
amount of time for the second data block as it previously did for the
third (and subsequent) blocks.
2017-12-29 23:56:32 +01:00
0a2d38ecd2
bios/sdram: use same initialization procedure for artix7 than kintex7 excepting write leveling that is not done
2017-12-29 17:13:58 +01:00
b78a4760bb
soc/integration/builder: don't build bios is user is providing rom data
2017-12-28 22:42:58 +01:00
5d98a60e6e
Merge pull request #38 from cr1901/mercury
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Add Mercury baseboard support from Migen, import fixes.
2017-12-27 17:52:37 +01:00
9adcc3a8b9
Merge pull request #37 from bunnie/add_tracelength
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Add tracelength report generation by default to help with board layout
2017-12-27 15:44:41 +01:00
282f22f09e
Add tracelength report generation by default to help with board layout
2017-12-27 22:40:39 +08:00
b463b2169b
boards/platforms/tinyfpga_b: add defaut serial pins
2017-12-27 00:26:30 +01:00
fe2564e921
build/lattice/icestorm: fix missing toolchain_path
2017-12-27 00:26:07 +01:00
5a2c92ba80
Add TinyFPGA platform based on Migen.
2017-12-27 00:00:05 +01:00
f096030fc8
Import Icestorm backend improvements from Migen.
2017-12-26 23:57:13 +01:00
e7015e4191
soc/integration/soc_core: add uart_name parameters (allow selecting uart without modifications in platform file)
2017-12-26 18:11:47 +01:00
a3390bb403
build/xilinx/programmer: fix settings in run_vivado (update)
2017-12-19 10:29:29 +01:00
dd6ca87561
Add Mercury baseboard support from Migen, import fixes.
2017-12-18 19:30:25 -05:00
4c82eb549f
build/xilinx: add support for edif/ngc files
2017-12-16 13:20:45 +01:00
b31d0f37db
cpu/picorv32: adapt to current version, some cleanup
2017-12-10 03:01:53 +01:00
4239aff68a
cpu: cleanup wrappers
2017-12-10 02:52:01 +01:00
43429560d4
soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code
2017-12-08 10:18:01 +01:00
27d37fa95d
targets/sim: fix
2017-12-06 22:22:05 +01:00
284b16e2c1
soc/integration/soc_core: make nmi interrupt optional
2017-12-03 23:07:41 +01:00
c1eba9a6cc
soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware
2017-11-24 13:16:58 +01:00
831b489fd3
soc/interconnect/stream: fix specific cases for last/first signal in UpConverter
2017-11-23 17:58:02 +01:00
06edd9c45c
Merge pull request #36 from mattkelly/fix-readme-typo
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Fix typo in README: experimental
2017-11-08 18:51:49 -08:00
0dfeeb58f6
Fix typo in README: experimental
2017-11-08 21:42:07 -05:00
c3d902ef42
soc/software/bios/sdram: add Kintex Ultrascale support
2017-11-08 12:59:38 +01:00
dcae61b6de
README: update copyrights
2017-11-01 21:12:42 +01:00
2665a83288
soc/interconnect/stream: expose depth on SyncFIFO
2017-10-30 22:56:09 +01:00
876f3d2c8f
Merge pull request #34 from mithro/uart-irq-change
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Change the default IRQs.
2017-10-30 13:54:19 -07:00
Felix Held
Tim Ansell
Chris Ballance
enjoy-digital
William D. Jones
Tim 'mithro' Ansell
Greg Darke
bunnie
Matt Kelly