dcdf5df4de
adapt LiteEth to new SoC
2015-04-01 22:50:29 +02:00
f65c0a3c95
adapt LiteScope to new SoC
2015-04-01 22:46:24 +02:00
2d23ab7a85
soc/sdram: fix do_finalize
2015-04-01 22:38:04 +02:00
2900429e65
soc: use set
2015-04-02 00:14:56 +08:00
369086a178
soc: simplify integrated memory parameters
2015-04-02 00:09:38 +08:00
273242b399
soc/sdram: minor cleanup
2015-04-01 23:41:55 +08:00
6e2a662dd7
litesata: adapt to new SoC API
2015-04-01 17:37:53 +08:00
9599eb6fae
soc: remove cpu_boot_file argument
2015-04-01 17:32:45 +08:00
fb86445d14
soc: remove cpu_or_bridge and with_cpu arguments
2015-04-01 17:29:51 +08:00
a148af97ba
soc: retrieve csr and memory regions using methods
2015-04-01 16:49:32 +08:00
8b19a11cd7
soc: use add_wb_master function
2015-04-01 15:56:54 +08:00
2a1112b912
soc: simplify/fix csr busword
2015-04-01 15:48:56 +08:00
04f29e97e2
soc: remove unnecessary imports
2015-04-01 15:15:09 +08:00
5113301130
soc: improve memory region conflict check
2015-04-01 15:14:02 +08:00
980791e2b8
soc: remove ns function
2015-04-01 14:33:12 +08:00
e5ddd1263c
remove redundant xilinx_strace_tailor.sh
2015-03-30 18:58:34 +02:00
b469571afe
move xilinx_strace_tailor to tools
2015-03-30 19:42:11 +08:00
c169f0b189
Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
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This reverts commit f03aa76292
2015-03-30 19:41:16 +08:00
dc88295338
Revert "migen/fhdl: pass fdict filename --> contents to specials"
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This reverts commit ea04947519
2015-03-30 19:41:13 +08:00
b1c811a3d1
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
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This reverts commit 95cfc444e6
2015-03-30 19:41:04 +08:00
15e24b6c10
mibuild/platforms: fix minispartan6
2015-03-30 11:42:14 +02:00
95cfc444e6
migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
2015-03-30 11:37:59 +02:00
ea04947519
migen/fhdl: pass fdict filename --> contents to specials
2015-03-30 11:37:57 +02:00
f03aa76292
migen: create VerilogConvert and EDIFConvert classes and return it with convert functions
2015-03-30 11:37:55 +02:00
21c5fb6f6c
Merge branch 'master' of github.com:m-labs/migen
2015-03-30 00:52:15 +08:00
19a6157478
platforms/lx9_microboard,usrp_b100: fix bitgen opts
2015-03-30 00:44:56 +08:00
263fc47728
platforms/kc705: fix .bin generation with ISE and Vivado
2015-03-29 21:15:20 +08:00
b313772a0c
sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
2015-03-29 12:34:40 +02:00
17f3590a7c
platforms/kc705: add iMPACT programmer
2015-03-29 12:15:39 +02:00
be20fbabe4
soc: limit main_ram_size to 256MB (we should modify mem_map to allow larger memories, this was the probably ARTIQ runtime issue....!!)
2015-03-28 23:35:44 +01:00
0649ded5fd
soc: simplify main_ram_size computation and share it between LASMIcon and Minicon
2015-03-28 23:10:33 +01:00
a8d91c0c1d
sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
2015-03-28 16:35:15 +01:00
75ee8a5db9
sdram/phy/simphy: OK with DDR3
2015-03-28 01:59:55 +01:00
51ce7cad6f
sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
2015-03-28 01:18:35 +01:00
a95b3f8f13
sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
2015-03-28 01:17:50 +01:00
7fe748e1b0
sdram/module: clean up tREFI. (use 64ms/8k or 4k)
2015-03-28 01:09:21 +01:00
54a88da5b8
Merge branch 'master' of https://github.com/m-labs/misoc
2015-03-27 19:22:29 +01:00
72fae61525
Merge branch 'master' of https://github.com/m-labs/migen
2015-03-27 19:22:03 +01:00
20b646bd1a
add tool to build minimal xilinx toolchains
2015-03-27 19:21:47 +01:00
54c14c7119
pipistrello: add por reset counter
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* this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works
2015-03-27 19:18:11 +01:00
f4c35e358e
software/bios/sdram: small clean up
2015-03-27 18:24:19 +01:00
6245dd7b6f
software/bios/sdram: for now desactivate random on address test since it seems to trigger a L2 cache or LASMIcon bug on at least de0nano/minispartan6
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Memtest sometimes reports 1 or 2 errors with de0nano/minispartan6 on this new test when used with LASMICON. Minicon seems fine. We will have to investigate on this issue.
2015-03-27 16:43:22 +01:00
f85a4f004b
software/bios/sdram: add random addressing to memtest
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testing memories with linear access is not good enough. Adding random addressing allow us to detect more eventual issues on our L2 cache or SDRAM controller.
2015-03-27 15:49:16 +01:00
ec080479da
mibuild/sim: use the same architecture we use for others backends
2015-03-27 14:14:49 +01:00
340014dbac
targets: revert use of integers in clocks/timings
2015-03-26 23:45:35 +01:00
9137b91e9e
sdram: remove nbits from modules and databits from GeomSettings
2015-03-26 23:27:37 +01:00
38d24b637e
software/bios/sdram: make seed_to_data static
2015-03-26 23:05:20 +01:00
9a9af17aca
sdram/phy/simphy: remove use of iter
2015-03-26 23:02:23 +01:00
e6de4b1bf9
sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
2015-03-26 22:28:32 +01:00
e79a716425
software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter)
2015-03-26 22:16:31 +01:00
Florent Kermarrec
Sebastien Bourdeauducq
Robert Jordens