developandplay
e0352a1f0f
Sync ROM_BOOT_ADDRESS with main_ram location
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Rocket and Blackparrot main_ram starts at 0x80000000
Vexriscv main_ram starts at 0x40000000
2021-06-09 03:36:32 +02:00
Florent Kermarrec
25ead1ad69
interconnect/stream: Add Gate.
2021-06-08 18:58:08 +02:00
Florent Kermarrec
bd1463514b
litex_setup: Remove Travis specific code (CI no longer run on Travis).
2021-06-08 10:49:28 +02:00
developandplay
f2caeaf83a
Fix base_address for LiteDRAMWishbone2Native
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Fixes `origin == None` due to https://github.com/litex-hub/litex-boards/commit/ba01776
2021-06-08 00:51:11 +02:00
Raptor Engineering Development Team
47c19933fa
Add 1920x1200@60 RBv2 to LiteX video modes Tested on Raptor Sparrowhawk
2021-06-07 14:49:33 -05:00
Florent Kermarrec
a064e9d048
soc/interconnect/wishbone: Fix SEL propagation on UpConverter (thanks @Dolu1990).
2021-06-02 10:46:53 +02:00
Florent Kermarrec
0b329c3dce
tools/litex_json2dts: Add initial USB OHCI support.
2021-06-01 10:41:35 +02:00
Florent Kermarrec
acebc949c6
litex_setup: Add USB OHCI pythondata.
2021-06-01 10:29:49 +02:00
Florent Kermarrec
a17ded2ce6
soc/cores: Add initial USB OHCI core wrapper.
2021-06-01 10:28:30 +02:00
Florent Kermarrec
6c8e839cef
soc/cores/freqmeter: Minor simplification.
2021-06-01 10:26:27 +02:00
Florent Kermarrec
26db10701a
integration/soc/add_video_terminal: Connect UART to TX FIFO instead of Source.
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Allow UART to be displayed on terminal with Auto TX flush.
2021-05-28 11:11:49 +02:00
Florent Kermarrec
ad1fe143cc
cores/uart: Cleanup code and add optional automatic TX Flush.
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In some SoCs where UART's PHY is managed externally (ex through a Bridge) we don't
necessarily want the UART TX to wait for the PHY to be ready (and then stall the
CPU) but just want to let the CPU print the UART and will just connect when useful
and handle backpressure when connected.
This is now possible by calling add_auto_tx_flush method, ex in the SoC:
self.uart.add_auto_tx_flush(sys_clk_freq)
2021-05-28 11:03:23 +02:00
Florent Kermarrec
f6b2135cc9
test/test_timer: Update.
2021-05-27 19:37:51 +02:00
Florent Kermarrec
d11dc0b503
libbase/memtest: Print size with 1 digit after the decimal point.
2021-05-27 19:33:29 +02:00
enjoy-digital
9b85769499
Merge pull request #923 from gsomlo/gls-fix-gcc-warn
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software/lib*: address gcc warnings
2021-05-27 18:50:24 +02:00
enjoy-digital
d7f4293743
Merge pull request #924 from developandplay/patch-2
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Use add_etherbone in simulation
2021-05-27 18:49:45 +02:00
Florent Kermarrec
34df454157
cores/timer/uart: Use edge="rising on Timer/UART's EventSourceProcess.
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Make code easier to understand.
2021-05-27 18:47:40 +02:00
Gabriel Somlo
9a24034d1d
software/lib*: address gcc warnings
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Fix gcc warnings: use 'unsigned long' to represent memory addresses,
and remove 'static' from the definition of 'cdelay()', as it is called
from multiple C files.
2021-05-27 08:47:29 -04:00
developandplay
c17421bccb
Use add_etherbone in simulation
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Fixes not working analyzer example from wiki
2021-05-26 23:18:22 +02:00
Florent Kermarrec
5fd215fe3a
soc/interconnect/stream/Pipeline: Improve comments.
2021-05-26 18:34:22 +02:00
Florent Kermarrec
b1d8fe61f8
cores/cpu: Add initial FemtoRV support.
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FemtoRV is a minimalist RISC-V CPU with design process documented and
available at https://github.com/BrunoLevy/learn-fpga .
This CPU is a very nice way to discover/learn RISC-V and this LiteX support
can be useful to learn how to integrate a custom CPU with LiteX.
With this support, FemtoRV is now directly usable with LiteX Sim:
$litex_sim --cpu-type=femtorv
This should also enable its use on all boards (> 50) available in LiteX-Boards
repository (but hasn't been tested yet), ex:
$python3 -m litex_boards.targets.digilent_arty --cpu-type=femtorv --build
2021-05-26 09:08:41 +02:00
Florent Kermarrec
d3560e5772
liblitedram/sdram.c: Update sdram_write_read_check_test_pattern with SDRAM_PHY_ECP5DDRPHY.
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The return value has been changed and also required to be update for SDRAM_PHY_ECP5DDRPHY.
2021-05-25 10:28:56 +02:00
enjoy-digital
8085cc3c97
Merge pull request #915 from zyp/liblitespi_remove_mode
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software/liblitespi: Remove manual mode control.
2021-05-25 08:41:13 +02:00
Romain Dolbeau
c06bd2c77d
Make the [ID]TLB size configurable from Litex ; expand the DTS to include cache/TLB/topology in CPUs & generate the required information for VexRiscv
2021-05-23 03:15:02 -04:00
Florent Kermarrec
5e40709cbc
README.md: IRC channel moved to moved to irc.libera.chat ( https://libera.chat ) #litex due to staff issues.
2021-05-22 12:15:24 +02:00
Florent Kermarrec
55344b4c14
cores/clock/xilinx: Add power down support.
2021-05-19 22:31:35 +02:00
Florent Kermarrec
cbb75b852e
cores/clock/xilinx: Cosmetic cleanup on Instances.
2021-05-19 22:20:04 +02:00
Florent Kermarrec
12b27f961c
software/liblitedram: Fix compilation on designs without SDRAM.
2021-05-19 11:07:03 +02:00
Florent Kermarrec
aa2622b1f5
software/liblitedram: Add missing #ifdef SDRAM_DEBUG to fix compilation with large DRAMs.
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sdram_dbg seems to have current limitations: "At most 32 databits SDR or 16 databits DDR supported".
2021-05-18 11:36:19 +02:00
enjoy-digital
beac24b796
Merge pull request #918 from antmicro/jboc/sdram-leveling
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Attempt to improve DRAM leveling robustness
2021-05-18 10:38:25 +02:00
enjoy-digital
4886623df6
Merge pull request #917 from antmicro/jboc/sdram-dbg
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Add utilities for debugging DRAM problems
2021-05-18 10:31:33 +02:00
enjoy-digital
ccc2550426
Merge pull request #916 from antmicro/jboc/memtest-config
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Make memtest_data more configurable
2021-05-18 10:22:15 +02:00
Jędrzej Boczar
93f357d853
soc/software/liblitedram: make leveling scores more robust by counting number of bitslips
2021-05-17 14:53:04 +02:00
Jędrzej Boczar
50805797c6
soc/software/liblitedram: optional write latency calibration debug output
2021-05-17 14:49:30 +02:00
Jędrzej Boczar
1f2b8621fe
soc/software/liblitedram: add sdram_debug command
2021-05-17 14:38:35 +02:00
Jędrzej Boczar
e5c1482572
soc/software/liblitedram: add sdram debugging utilities
2021-05-17 14:19:16 +02:00
Jędrzej Boczar
cd6f98c4c8
soc/software/liblitedram: use updated sdram_dfii_pix_X_addr interface
2021-05-17 14:11:10 +02:00
Jędrzej Boczar
33fb48584b
soc/software/libbase: add option for read retries in memtest_data
2021-05-17 13:56:31 +02:00
Jędrzej Boczar
d610c9da44
soc/software/libbase: limit number of errors printed when using MEMTEST_*_DEBUG
2021-05-17 13:53:32 +02:00
Vegard Storheil Eriksen
422c356930
software/liblitespi: Remove manual mode control.
2021-05-17 13:44:02 +02:00
Jędrzej Boczar
b90d0bd1f7
soc/software/libbase: make memtest_data more configurable, add on_error callback
2021-05-17 13:42:44 +02:00
Florent Kermarrec
13979a43b7
soc/add_cpu: Fix/Simplify CFU integration.
2021-05-17 12:04:37 +02:00
Florent Kermarrec
d0e8de077c
soc/SoCController: Add separate fields for SoC and CPU resets.
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As discussed in #909 , in some specific cases, it can be interesting to be able
to keep the CPU in reset while the rest of the SoC is still operating (ex the
peripherals/bridges).
With theses changes, the old behaviour is preserved to do a full SoC Reset (at
the exception that writing a 1 is now mandatory) and a separate field specific
to the CPU reset is added.
The SoC Reset is a pulse (otherwise the system would be stuck in Reset) while
the CPU Reset is based on the register value (so can be pulse or hold).
2021-05-17 11:43:04 +02:00
Florent Kermarrec
06f4658174
cpu: Specify clock domain (improve readability).
2021-05-17 10:51:54 +02:00
Florent Kermarrec
78bdde0424
cpu/vexriscv: Simplify CFU integration, use Cfu.v as default CFU when not specified and rename argument to --cpu-cfu.
2021-05-17 10:02:58 +02:00
Florent Kermarrec
87bb10f43b
CHANGES: Start listing changes for next release.
2021-05-17 09:58:46 +02:00
Florent Kermarrec
a6c37df175
soc_core: Improve readability and move ROM initialization to SoCCore. (--integrated-rom-file args is also renamed to --integrated-rom-init to simplify support for str and list).
2021-05-17 09:55:28 +02:00
Florent Kermarrec
dd72b1acfe
soc/add_cpu: Add **kwargs support.
2021-05-17 09:53:40 +02:00
Florent Kermarrec
298f65e78e
cpu/vexriscv: Change methods' order to improve readability.
2021-05-17 08:54:53 +02:00
enjoy-digital
fc0e1440c5
Merge pull request #908 from antmicro/cfu-integration
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Add CFU integration
2021-05-17 08:43:38 +02:00