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litex
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173 Commits 42 Branches 14 Tags 30 MiB
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173 Commits

Author SHA1 Message Date
Florent Kermarrec 2bb9c6b649 add verilog backend to use the core with a "standard" flow 2015-01-19 20:38:48 +01:00
Florent Kermarrec d84ae7c80c clean up 2015-01-19 18:13:43 +01:00
Florent Kermarrec 18f2933d8b add doc skeleton (from emscripten with readthedocs theme) 2015-01-19 17:10:24 +01:00
Florent Kermarrec 79dbb6da4b replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows) 2015-01-19 09:45:34 +01:00
Florent Kermarrec 6de7e15a0c refactor code 2015-01-17 13:22:52 +01:00
Florent Kermarrec 6f2c7a236c add support of identify device command 2015-01-17 02:35:25 +01:00
Florent Kermarrec c227576f3d add test_link.py (replace test_bist_mila) 2015-01-16 21:16:05 +01:00
Florent Kermarrec 175618bcb4 use csr_data_width of 32 to speed up data mila upload 2015-01-16 20:57:01 +01:00
Florent Kermarrec 083bd54121 global clean up 
- remove initial sims
- remove SATAPHYDeviceCtrl
- rename to LiteSATA
- rename test to bist
 2015-01-16 20:26:15 +01:00
Florent Kermarrec e90d97e9c2 phy: remove GTXE2_COMMON (no longer need since it was a Vivado bug that is now fixed) 2015-01-16 19:25:35 +01:00
Florent Kermarrec d13366dd2d bist: use hardware counter for speed calc and remove loops mode 2015-01-16 18:48:34 +01:00
Florent Kermarrec 7ccc5f5274 link/cont: improve timing 2015-01-16 18:13:07 +01:00
Florent Kermarrec 1170a1070b add need_reset from controller to request system reset when SATA is not locked 2015-01-15 00:56:47 +01:00
Florent Kermarrec 788546c6ae add frontend and improve BIST 2015-01-14 15:47:13 +01:00
Florent Kermarrec 62f55e32cf use new submodules/specials/clock_domains automatic collection 2015-01-12 13:14:26 +01:00
Florent Kermarrec 4f38b0ef6e improve timings with BufferizeEndpoints 2015-01-08 22:59:31 +01:00
Florent Kermarrec d196a517d6 use 166MHz clock 2015-01-08 22:58:26 +01:00
Florent Kermarrec 4deda89dcb simplify bist 2015-01-07 22:15:57 +01:00
Florent Kermarrec 1c03f72252 command: add robustness and simplify RX path 2015-01-07 18:49:10 +01:00
Florent Kermarrec aed1064465 command: replace SyncFIFO with Buffer for cmd_buffer 2015-01-06 17:03:27 +01:00
Florent Kermarrec a450079866 command: add support for larger DMAs 2015-01-06 16:48:19 +01:00
Florent Kermarrec c08c0ffc4e link: check CRC on RX path 2014-12-25 17:15:35 +01:00
Florent Kermarrec 5575ecbcb2 test: fix link_tb and bist_tb 2014-12-25 12:28:06 +01:00
Florent Kermarrec aa8c0c983c add option to implement or not mila (to see real ressource usage of the SATA controller) 2014-12-24 15:57:42 +01:00
Florent Kermarrec 7efaef485f command: remove returns to IDLE state (will be better to add a timeout for a transfer and reset the fsm). 2014-12-24 15:08:06 +01:00
Florent Kermarrec 8b1522bbc9 clean up TestDesign 2014-12-24 15:05:17 +01:00
Florent Kermarrec 7df1d75dee use max_count of 16 and clean up 2014-12-23 23:19:48 +01:00
Florent Kermarrec 74dd907503 add test_bist_mila to show how to capture data 2014-12-23 21:00:38 +01:00
Florent Kermarrec db711edd89 add test_bist with mila 2014-12-23 20:41:35 +01:00
Florent Kermarrec 3e5a4ab097 add wr_only and rd_only mode to BIST (to test speed) and switch to 100MHz system clock 2014-12-23 20:41:13 +01:00
Florent Kermarrec 678ee33af4 improve BIST and clean up (remove support of identify command and debug code) 2014-12-23 19:27:52 +01:00
Florent Kermarrec 38d3f3697b test bist at high speed(working) 2014-12-23 01:39:41 +01:00
Florent Kermarrec 46b2d02783 test bist at slow speed (working) 2014-12-23 00:41:39 +01:00
Florent Kermarrec 6b12782816 read/write seems OK with CommandGenerator 2014-12-23 00:08:22 +01:00
Florent Kermarrec 5e513c25c2 link: fix rx path 2014-12-22 20:58:38 +01:00
Florent Kermarrec c17159754c add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems to be stuck in link of command layer) 2014-12-20 16:50:34 +01:00
Florent Kermarrec eebc2abcda add mode generic CommandGenerator for debug 2014-12-20 16:21:26 +01:00
Florent Kermarrec 9dc6903c55 add identify device to command_tb and revert endianness (seems conform with Lecroy SATA Protocol suite samples) 
it seems endianness is correct by is only printed in LSB first in Lecroy software
 2014-12-20 13:26:07 +01:00
Florent Kermarrec 706fcb536d change FIS endianness (seems to be little endian) 2014-12-20 12:58:37 +01:00
Florent Kermarrec f495639f22 add primitives decoding in test_identify to ease debug 2014-12-20 01:26:58 +01:00
Florent Kermarrec d368a89bbf fix ack in idle in some fsm (implementation behaviour different from simulation) 2014-12-20 01:26:02 +01:00
Florent Kermarrec 35050ece9f add fsms to mila for debug 2014-12-20 00:03:03 +01:00
Florent Kermarrec 68a7ff6dc2 use new submodules collection to expose more fsm an modules 2014-12-19 22:50:35 +01:00
Florent Kermarrec ea245542c6 link: add parameter to disable CONT insertion (will ease debug) 2014-12-19 22:32:11 +01:00
Florent Kermarrec ea2b06b285 fix phy datapath, first communications between SATACON and a HDD... :) 2014-12-19 22:20:41 +01:00
Florent Kermarrec a79696641a prepare identify test with SATACON 2014-12-19 19:05:49 +01:00
Florent Kermarrec 880c7e7ecc test: change UART baudrate and test SATACONTRemover 2014-12-19 17:45:02 +01:00
Florent Kermarrec 33eed1aa79 SATAPHYDatapathRX: use Converter and simplify 2014-12-19 17:27:44 +01:00
Florent Kermarrec 0ab7ca6f28 SATAPHYDatapathTX: use Converter and simplify 2014-12-19 17:13:03 +01:00
Florent Kermarrec 8bb40241fa add phy_datapath_tb and start datapath simplification 2014-12-19 16:48:22 +01:00