Sergiusz Bazanski
7ea5a26734
Enable hardware multiplier and divider in PicoRV32
...
This should become tunable later once we can configure whether we link
in the soft mul library or not.
2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
20ed23443b
Export trap signal from PicoRV32.
...
This is useful for handling crashes from hardware.
2018-01-22 18:50:26 +00:00
Sergiusz Bazanski
b0be563012
Bump PicoRV32 version.
2018-01-22 18:50:26 +00:00
Felix Held
6318a2b29a
Fix all remaining indentation issues in python code
...
I ran a script that shouldn't have missed any tab in the python source files.
2018-01-13 13:19:36 +11:00
Tim 'mithro' Ansell
44650dffd8
cpu: Adding "variant" support.
...
It is useful to support slightly different variants of the CPU
configurations. This adds a "cpu_variant" option.
For the mor1k we now have the default mor1k configuration and the
"linux" variant which enables the features needed for Linux support on
the mor1k.
Currently there are no variants for the lm32, but we will likely add a
"tiny" variant for usage on the iCE40.
2017-12-30 01:18:51 +01:00
Florent Kermarrec
b31d0f37db
cpu/picorv32: adapt to current version, some cleanup
2017-12-10 03:01:53 +01:00
Florent Kermarrec
4239aff68a
cpu: cleanup wrappers
2017-12-10 02:52:01 +01:00
Florent Kermarrec
ba1bf20f37
soc/cores: add cordic
2017-09-29 12:07:43 +02:00
Florent Kermarrec
c02de1632b
soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists
2017-07-27 18:22:01 +02:00
Florent Kermarrec
bdea4152e3
soc/core/uart: add UartStub to enable fast simulation with cpu
2017-07-06 19:19:10 +02:00
Florent Kermarrec
1364ac3657
soc/cores/identifier: append 0 to contents to indicate end of string
2017-06-22 17:53:19 +02:00
Florent Kermarrec
c19c4b711b
soc/cores/identifier: remove additionnal first character
2017-06-08 14:15:27 +02:00
Florent Kermarrec
77732fca95
soc/cores/uart: add uart multiplexer
2017-06-05 19:36:30 +02:00
Florent Kermarrec
85aea62d74
soc/core: add frequency meter
2017-06-01 00:39:19 +02:00
Florent Kermarrec
4bc6cf6165
soc/cores: dna/xadc: add missing copyright
2017-05-16 21:18:32 +02:00
Florent Kermarrec
9350a7b5e6
soc/cores: add dna and xadc (for 7-series, add support for others fpgas?)
2017-05-16 21:02:33 +02:00
Florent Kermarrec
b34f74397a
soc/cores: add code_8b10b from misoc
2017-04-19 11:05:21 +02:00
Florent Kermarrec
9cfc594280
soc/cores: move flash cores to cores directory
2017-04-19 10:58:15 +02:00
Florent Kermarrec
e1319924aa
soc: move uart to a single file
2017-04-19 10:37:59 +02:00
Florent Kermarrec
1acca39397
soc/cores: add new spi master, remove obsolete one
2017-04-19 10:22:35 +02:00
Florent Kermarrec
790020de9f
soc/cores/flash/spi_flash: remove bitbanging comment (no longer supported)
2017-02-01 12:21:56 +01:00
Florent Kermarrec
4b77b850ce
add SpiFlashSingle and rename SpiFlash to SpiFlashDualQuad
2017-01-26 13:28:18 +01:00
Sebastien Bourdeauducq
e39c470bbc
spi_flash: fix bitbang with spi_width=1
2016-12-26 14:11:49 +01:00
Florent Kermarrec
66362b1280
move sdram code to litedram ( https://github.com/enjoy-digital/litedram )
2016-04-29 07:45:15 +02:00
Florent Kermarrec
3d98be0997
use new Record.connect omit parameter (replace leave_out)
2016-04-21 09:39:21 +02:00
Florent Kermarrec
5ba03160ed
soc/cores: fix spi
2016-04-19 06:49:23 +02:00
Florent Kermarrec
429f533bd0
soc/cores/sdram/settings: simplify modules and fix timing margins computation
2016-04-18 18:22:53 +02:00
Florent Kermarrec
9fa9bdcf68
build/sim: adapt verilator simulation to new stream signals
2016-04-07 08:56:53 +02:00
Florent Kermarrec
17f6cb1f17
initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)
2016-04-01 00:09:17 +02:00
Florent Kermarrec
b8d89535fd
soc/cores/sdram/phy: fix S6QuarterRateDDRPHY
2016-03-29 14:59:30 +02:00
Florent Kermarrec
71a719be44
soc/interconnect/stream: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
2016-03-16 20:13:47 +01:00
Florent Kermarrec
e0e2427795
soc: replace all Sink/Source with stream.Endpoint
2016-03-16 18:05:57 +01:00
Florent Kermarrec
0498a31818
some cleanup
...
- remove Sink/Source connect specialization.
- remove use of Record.connect
- use sink/source on Buffer
2015-12-27 13:09:58 +01:00
Florent Kermarrec
1cde84dccf
soc/cores/uart remove software (will be re-written and will move to soc/tools)
2015-11-16 17:07:22 +01:00
Florent Kermarrec
7ed2576ce1
soc/integration/cpu_interface: add bases, constants and memories output to csv files
2015-11-15 00:04:44 +01:00
Florent Kermarrec
af909b43d5
soc/cores/uart: add UARTWishboneBridgeDriver software
2015-11-14 21:23:20 +01:00
Florent Kermarrec
a2aa5726bf
soc/cores: remove liteeth_mini and use liteeth
2015-11-14 03:22:43 +01:00
Florent Kermarrec
fc3ffe87ac
for now use our fork of migen (to be able to simulate our designs)
2015-11-13 18:31:46 +01:00
Florent Kermarrec
525da89c7d
soc/interconnect: add wishbonebridge and uart bridge
2015-11-12 00:52:36 +01:00
Florent Kermarrec
1f6983da2c
soc/cores/liteeth_mini: add phy model for verilator simulation
2015-11-11 14:22:27 +01:00
Florent Kermarrec
481163b233
soc/cores: reintroduce liteeth_mini (until we switch to liteeth)
2015-11-11 14:01:48 +01:00
Florent Kermarrec
619cd8e695
avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
2015-11-11 12:10:55 +01:00
Florent Kermarrec
3f43a49382
soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b
...
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
2015-11-10 16:51:51 +01:00
Florent Kermarrec
3297210e48
boards/targets/sim: get SDRAM working in simulation with sdram/model
2015-11-10 12:57:23 +01:00
Florent Kermarrec
a775672314
litex: get verilator simulation working and add sim target as example
2015-11-07 23:51:37 +01:00
Florent Kermarrec
6a0f85dc42
litex: reorganize things, first work working version
2015-11-07 17:48:55 +01:00
